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[Qemu-commits] [qemu/qemu] f3b423: target/hppa: Check for page crossings

From: Peter Maydell
Subject: [Qemu-commits] [qemu/qemu] f3b423: target/hppa: Check for page crossings in use_goto_tb
Date: Wed, 13 Mar 2019 04:43:47 -0700 
  Branch: refs/heads/master
  Home:   https://github.com/qemu/qemu
  Commit: f3b423ec6ee4123fedbb74db517262dd14fa4d73
      
https://github.com/qemu/qemu/commit/f3b423ec6ee4123fedbb74db517262dd14fa4d73
  Author: Richard Henderson <address@hidden>
  Date:   2019-03-12 (Tue, 12 Mar 2019)

  Changed paths:
    M target/hppa/translate.c

  Log Message:
  -----------
  target/hppa: Check for page crossings in use_goto_tb

We got away with eliding this check when target/hppa was user-only,
but missed adding this check when adding system support.

Fixes an early crash in the HP-UX 11 installer.

Reported-by: Sven Schnelle <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>


  Commit: 43675d20150e65a5a45923a6fcd292e80006dad0
      
https://github.com/qemu/qemu/commit/43675d20150e65a5a45923a6fcd292e80006dad0
  Author: Sven Schnelle <address@hidden>
  Date:   2019-03-12 (Tue, 12 Mar 2019)

  Changed paths:
    M target/hppa/translate.c

  Log Message:
  -----------
  target/hppa: fix overwriting source reg in addb

When one of the source registers is the same as the destination register,
the source register gets overwritten with the destionation value before
do_add_sv() is called, which leads to unexpection condition matches.

Signed-off-by: Sven Schnelle <address@hidden>
Message-Id: <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>


  Commit: 0b49c3398851622ead40c7e1fc3144d3187123fd
      
https://github.com/qemu/qemu/commit/0b49c3398851622ead40c7e1fc3144d3187123fd
  Author: Sven Schnelle <address@hidden>
  Date:   2019-03-12 (Tue, 12 Mar 2019)

  Changed paths:
    M target/hppa/mem_helper.c

  Log Message:
  -----------
  target/hppa: fix TLB handling for page 0

Assume the following sequence:

pitlbe r0(sr0,r0)
iitlba r4,(sr0,r0)
ldil L%3000000,r5
iitlbp r5,(sr0,r0)

This will purge the whole TLB and add an entry for page 0. However
the current TLB implementation in helper_iitlba() will store to
the last empty TLB entry, while helper_iitlbp() will write to the
first empty entry. That is because an empty entry will match address
0 in helper_iitlba()

Signed-off-by: Sven Schnelle <address@hidden>
Message-Id: <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>


  Commit: acd6ba74d6de7add51763a19e6af2f0e41877513
      
https://github.com/qemu/qemu/commit/acd6ba74d6de7add51763a19e6af2f0e41877513
  Author: Sven Schnelle <address@hidden>
  Date:   2019-03-12 (Tue, 12 Mar 2019)

  Changed paths:
    M target/hppa/mem_helper.c

  Log Message:
  -----------
  target/hppa: report ITLB_EXCP_MISS for ITLB misses

Signed-off-by: Sven Schnelle <address@hidden>
Message-Id: <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>


  Commit: 23c3d569f44284066714ff7c46bc4f19e630583f
      
https://github.com/qemu/qemu/commit/23c3d569f44284066714ff7c46bc4f19e630583f
  Author: Sven Schnelle <address@hidden>
  Date:   2019-03-12 (Tue, 12 Mar 2019)

  Changed paths:
    M Makefile.objs
    M target/hppa/mem_helper.c
    M target/hppa/op_helper.c
    A target/hppa/trace-events

  Log Message:
  -----------
  target/hppa: add TLB trace events

To ease TLB debugging add a few trace events, which are disabled
by default so that there's no performance impact.

Signed-off-by: Sven Schnelle <address@hidden>
Message-Id: <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>


  Commit: b06c0618c08c96d045c99b1bc21b6ce8fbee9581
      
https://github.com/qemu/qemu/commit/b06c0618c08c96d045c99b1bc21b6ce8fbee9581
  Author: Sven Schnelle <address@hidden>
  Date:   2019-03-12 (Tue, 12 Mar 2019)

  Changed paths:
    M target/hppa/op_helper.c

  Log Message:
  -----------
  target/hppa: remove PSW I/R/Q bit check

HP ODE use rfi to set the Q bit, and i don't see anything in the
documentation that this is forbidden. So remove it.

Signed-off-by: Sven Schnelle <address@hidden>
Message-Id: <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>


  Commit: 15da177bb40aecd829f32354190eec759947dc30
      
https://github.com/qemu/qemu/commit/15da177bb40aecd829f32354190eec759947dc30
  Author: Sven Schnelle <address@hidden>
  Date:   2019-03-12 (Tue, 12 Mar 2019)

  Changed paths:
    M target/hppa/insns.decode
    M target/hppa/translate.c

  Log Message:
  -----------
  target/hppa: ignore DIAG opcode

DIAG is usually only used by diagnostics software as it's CPU
specific. In most of the cases it's better to ignore it and log
a message that it's not implemented.

Signed-off-by: Sven Schnelle <address@hidden>
Message-Id: <address@hidden>
[rth: Free the nullify condition.]
Signed-off-by: Richard Henderson <address@hidden>


  Commit: 6e5f530025116b0c8c41e1a775d4b1ec87e4bd73
      
https://github.com/qemu/qemu/commit/6e5f530025116b0c8c41e1a775d4b1ec87e4bd73
  Author: Sven Schnelle <address@hidden>
  Date:   2019-03-12 (Tue, 12 Mar 2019)

  Changed paths:
    M target/hppa/translate.c

  Log Message:
  -----------
  target/hppa: fix b,gate instruction

b,gate does GR[t] ← cat(GR[t]{0..29},IAOQ_Front{30..31});
instead of saving the link address to register t.

Signed-off-by: Sven Schnelle <address@hidden>
Message-Id: <address@hidden>
[rth: Move link check outside of ifndef CONFIG_USER_ONLY;
 use ctx->privilege; nullify the insn earlier.]
Signed-off-by: Richard Henderson <address@hidden>


  Commit: 38188fd216cf139e88459296cb42400b5a039f79
      
https://github.com/qemu/qemu/commit/38188fd216cf139e88459296cb42400b5a039f79
  Author: Sven Schnelle <address@hidden>
  Date:   2019-03-12 (Tue, 12 Mar 2019)

  Changed paths:
    M target/hppa/mem_helper.c

  Log Message:
  -----------
  target/hppa: allow multiple itlbp without itlba

The ODE software calls itlbp on existing TLB entries without
calling itlba first, so this seems to be valid.

Signed-off-by: Sven Schnelle <address@hidden>
Message-Id: <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>


  Commit: d5de20bd84ae3a6f6c194f0088cfcb4d4f6af602
      
https://github.com/qemu/qemu/commit/d5de20bd84ae3a6f6c194f0088cfcb4d4f6af602
  Author: Sven Schnelle <address@hidden>
  Date:   2019-03-12 (Tue, 12 Mar 2019)

  Changed paths:
    M target/hppa/cpu.h
    M target/hppa/gdbstub.c
    M target/hppa/helper.c
    M target/hppa/helper.h
    M target/hppa/mem_helper.c
    M target/hppa/translate.c

  Log Message:
  -----------
  target/hppa: add TLB protection id check

Signed-off-by: Sven Schnelle <address@hidden>
Message-Id: <address@hidden>
[rth: Add required tlb flushing when prot id registers change.]
Signed-off-by: Richard Henderson <address@hidden>


  Commit: 32dc75698c848d11a087c77570ac0cd954e0bb20
      
https://github.com/qemu/qemu/commit/32dc75698c848d11a087c77570ac0cd954e0bb20
  Author: Sven Schnelle <address@hidden>
  Date:   2019-03-12 (Tue, 12 Mar 2019)

  Changed paths:
    M target/hppa/translate.c

  Log Message:
  -----------
  target/hppa: exit TB if either Data or Instruction TLB changes

The current code assumes that we don't need to exit the TB
if a Data Cache Flush or Insert has happend. However, as we
have a shared Data/Instruction TLB, a Data cache flush also
flushes Instruction TLB entries, and a Data cache TLB insert
might also evict a Instruction TLB entry.

So exit the TB in all cases if Instruction translation is enabled.

Signed-off-by: Sven Schnelle <address@hidden>
Message-Id: <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>


  Commit: 9298a4e8a648d88300883681317ed733a6ad39d0
      
https://github.com/qemu/qemu/commit/9298a4e8a648d88300883681317ed733a6ad39d0
  Author: Peter Maydell <address@hidden>
  Date:   2019-03-13 (Wed, 13 Mar 2019)

  Changed paths:
    M Makefile.objs
    M target/hppa/cpu.h
    M target/hppa/gdbstub.c
    M target/hppa/helper.c
    M target/hppa/helper.h
    M target/hppa/insns.decode
    M target/hppa/mem_helper.c
    M target/hppa/op_helper.c
    A target/hppa/trace-events
    M target/hppa/translate.c

  Log Message:
  -----------
  Merge remote-tracking branch 'remotes/rth/tags/pull-hppa-20190312' into 
staging

Misc fixes affecting HP-UX 10.20.

# gpg: Signature made Tue 12 Mar 2019 16:16:32 GMT
# gpg:                using RSA key 64DF38E8AF7E215F
# gpg: Good signature from "Richard Henderson <address@hidden>" [full]
# Primary key fingerprint: 7A48 1E78 868B 4DB6 A85A  05C0 64DF 38E8 AF7E 215F

* remotes/rth/tags/pull-hppa-20190312:
  target/hppa: exit TB if either Data or Instruction TLB changes
  target/hppa: add TLB protection id check
  target/hppa: allow multiple itlbp without itlba
  target/hppa: fix b,gate instruction
  target/hppa: ignore DIAG opcode
  target/hppa: remove PSW I/R/Q bit check
  target/hppa: add TLB trace events
  target/hppa: report ITLB_EXCP_MISS for ITLB misses
  target/hppa: fix TLB handling for page 0
  target/hppa: fix overwriting source reg in addb
  target/hppa: Check for page crossings in use_goto_tb

Signed-off-by: Peter Maydell <address@hidden>


Compare: https://github.com/qemu/qemu/compare/3f3bbfc7cef4...9298a4e8a648
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