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[Qemu-commits] [qemu/qemu] 571a7e: target/xtensa/import_core.sh: don't a
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From: |
Peter Maydell |
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Subject: |
[Qemu-commits] [qemu/qemu] 571a7e: target/xtensa/import_core.sh: don't add duplicate ... |
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Date: |
Fri, 01 Mar 2019 01:39:38 -0800 |
Branch: refs/heads/master
Home: https://github.com/qemu/qemu
Commit: 571a7e34f956e0c7ce7fc26b31977be944a3dd94
https://github.com/qemu/qemu/commit/571a7e34f956e0c7ce7fc26b31977be944a3dd94
Author: Max Filippov <address@hidden>
Date: 2019-02-08 (Fri, 08 Feb 2019)
Changed paths:
M target/xtensa/import_core.sh
Log Message:
-----------
target/xtensa/import_core.sh: don't add duplicate 'static'
xtensa-modules.c produced by recent Tensilica tools have
Opcode_*_encode_fns arrays defined as static. Don't add extra 'static'
in front of them when importing.
Signed-off-by: Max Filippov <address@hidden>
Commit: fe7869d69caeb0d77b75d14051a6e72a6a10aa76
https://github.com/qemu/qemu/commit/fe7869d69caeb0d77b75d14051a6e72a6a10aa76
Author: Max Filippov <address@hidden>
Date: 2019-02-10 (Sun, 10 Feb 2019)
Changed paths:
M target/xtensa/cpu.h
M target/xtensa/helper.c
M target/xtensa/translate.c
Log Message:
-----------
target/xtensa: don't specify windowed registers manually
Use libisa to extract whether opcode uses windowed registers and
construct mask based on that. This only leaves special case for the
'entry' opcode, as it needs to probe a register dynamically.
Signed-off-by: Max Filippov <address@hidden>
Commit: 9791e7e91819468fa4009809fd340575f3fd3d12
https://github.com/qemu/qemu/commit/9791e7e91819468fa4009809fd340575f3fd3d12
Author: Max Filippov <address@hidden>
Date: 2019-02-11 (Mon, 11 Feb 2019)
Changed paths:
M target/xtensa/translate.c
Log Message:
-----------
target/xtensa: get rid of gen_callw[i]
Merge gen_callwi and gen_callw into their only users, translate_callw
and translate_callxw. Extract jump slot adjustment logic into a separate
function and use it in gen_jumpi and translate_callw.
Signed-off-by: Max Filippov <address@hidden>
Commit: 2012f47e2371537bf41a9347af6db1d3d675a1a4
https://github.com/qemu/qemu/commit/2012f47e2371537bf41a9347af6db1d3d675a1a4
Author: Max Filippov <address@hidden>
Date: 2019-02-18 (Mon, 18 Feb 2019)
Changed paths:
M target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c
Log Message:
-----------
target/xtensa: fixup test_mmuhifi_c3 overlay
xtensa-modules part of the test_mmuhifi_c3 core is missing fixes that
returns XTENSA_UNDEFINED for undefined opcodes and marks all data
structures static. Run sed script from target/xtensa/import_core.sh on
it. This fixes test_sr tests for missing special registers.
Signed-off-by: Max Filippov <address@hidden>
Commit: 0e7c887919e44f25491a4eb86403e947d9d54937
https://github.com/qemu/qemu/commit/0e7c887919e44f25491a4eb86403e947d9d54937
Author: Max Filippov <address@hidden>
Date: 2019-02-18 (Mon, 18 Feb 2019)
Changed paths:
M target/xtensa/cpu.h
M target/xtensa/helper.c
M target/xtensa/overlay_tool.h
Log Message:
-----------
target/xtensa: move xtensa_finalize_config to xtensa_core_class_init
Don't run xtensa_finalize_config at the time of core registration,
instead run it at the CPU class initialization.
Signed-off-by: Max Filippov <address@hidden>
Commit: 759039737504c3f11098f7240c6048c6279e2215
https://github.com/qemu/qemu/commit/759039737504c3f11098f7240c6048c6279e2215
Author: Max Filippov <address@hidden>
Date: 2019-02-18 (Mon, 18 Feb 2019)
Changed paths:
M target/xtensa/cpu.h
M target/xtensa/helper.c
M target/xtensa/translate.c
Log Message:
-----------
target/xtensa: don't require opcode table sorting
Requirement for alphabetical opcode sorting in opcode tables is awkward
and does not allow sharing implementation between multiple opcodes.
Use hash tables to find opcodes by name. Move implementation from the
translate.c to the helper.c to its only user and remove declaration from
the cpu.h
Signed-off-by: Max Filippov <address@hidden>
Commit: d863fcf7f5b4f363e7ba2f95ce622f93dd4e866d
https://github.com/qemu/qemu/commit/d863fcf7f5b4f363e7ba2f95ce622f93dd4e866d
Author: Max Filippov <address@hidden>
Date: 2019-02-18 (Mon, 18 Feb 2019)
Changed paths:
M target/xtensa/cpu.h
M target/xtensa/helper.c
M target/xtensa/translate.c
Log Message:
-----------
target/xtensa: allow multiple names for single opcode
There are opcodes that differ only in encoding or possible range of
immediate arguments. Allow multiple names for single opcode translation
table entry to reduce code duplication in that case.
Signed-off-by: Max Filippov <address@hidden>
Commit: fa6bc73c8b46782bf07dadcac908405cf19b8ab8
https://github.com/qemu/qemu/commit/fa6bc73c8b46782bf07dadcac908405cf19b8ab8
Author: Max Filippov <address@hidden>
Date: 2019-02-18 (Mon, 18 Feb 2019)
Changed paths:
M target/xtensa/translate.c
Log Message:
-----------
target/xtensa: implement wide branches and loops
FLIX adds branch and loop instruction variants with 15- and 18-bit wide
target offset. Implement them as additional names for the ordinary
branch/loop opcodes.
Signed-off-by: Max Filippov <address@hidden>
Commit: 20e9fd0fc0634de24ee2763d769e3780e369afdd
https://github.com/qemu/qemu/commit/20e9fd0fc0634de24ee2763d769e3780e369afdd
Author: Max Filippov <address@hidden>
Date: 2019-02-28 (Thu, 28 Feb 2019)
Changed paths:
M target/xtensa/cpu.h
M target/xtensa/translate.c
Log Message:
-----------
target/xtensa: sort FLIX instruction opcodes
Opcodes in different slots may read and write same resources (registers,
states). In the absence of resource dependency loops it must be possible
to sort opcodes to avoid interference.
Record resources used by each opcode in the bundle. Build opcode
dependency graph and use topological sort to order its nodes. In case of
success translate opcodes in sort order. In case of failure report and
raise invalid opcode exception.
Signed-off-by: Max Filippov <address@hidden>
Commit: 45b71a795e5add347f0ba7aba526896132e9b986
https://github.com/qemu/qemu/commit/45b71a795e5add347f0ba7aba526896132e9b986
Author: Max Filippov <address@hidden>
Date: 2019-02-28 (Thu, 28 Feb 2019)
Changed paths:
M target/xtensa/cpu.h
M target/xtensa/translate.c
Log Message:
-----------
target/xtensa: add generic instruction post-processing
Some opcodes may need additional actions at every exit from the
translated instruction or may need to amend TB exit slots available to
jumps generated for the instruction. Add gen_postprocess function and
call it from the gen_jump_slot and from the disas_xtensa_insn.
Signed-off-by: Max Filippov <address@hidden>
Commit: 8df3fd359697d68095c5f1ba47e83e8e237a3055
https://github.com/qemu/qemu/commit/8df3fd359697d68095c5f1ba47e83e8e237a3055
Author: Max Filippov <address@hidden>
Date: 2019-02-28 (Thu, 28 Feb 2019)
Changed paths:
M target/xtensa/cpu.h
M target/xtensa/helper.h
M target/xtensa/translate.c
M target/xtensa/win_helper.c
Log Message:
-----------
target/xtensa: move WINDOW_BASE SR update to postprocessing
Opcodes that modify WINDOW_BASE SR don't have dependency on opcodes that
use windowed registers. If such opcodes are combined in a single
instruction they may not be correctly ordered. Instead of adding said
dependency use temporary register to store changed WINDOW_BASE value and
do actual register window rotation as a postprocessing step.
Not all opcodes that change WINDOW_BASE need this: retw, rfwo and rfwu
are also jump opcodes, so they are guaranteed to be translated last and
thus will not affect other opcodes in the same instruction.
Signed-off-by: Max Filippov <address@hidden>
Commit: c949009bc0612cbfc7bc5b80c3e9ea3e24313434
https://github.com/qemu/qemu/commit/c949009bc0612cbfc7bc5b80c3e9ea3e24313434
Author: Max Filippov <address@hidden>
Date: 2019-02-28 (Thu, 28 Feb 2019)
Changed paths:
M target/xtensa/helper.h
M target/xtensa/translate.c
M target/xtensa/win_helper.c
Log Message:
-----------
target/xtensa: only rotate window in the retw helper
Move return address calculation and WINDOW_START adjustment out of the
retw helper to simplify logic a bit and avoid using registers directly.
Pass a0 as a parameter to the helper.
Signed-off-by: Max Filippov <address@hidden>
Commit: b0b24bdcd9dca02bd5d09e266892d261713cebe8
https://github.com/qemu/qemu/commit/b0b24bdcd9dca02bd5d09e266892d261713cebe8
Author: Max Filippov <address@hidden>
Date: 2019-02-28 (Thu, 28 Feb 2019)
Changed paths:
M target/xtensa/cpu.h
M target/xtensa/helper.c
M target/xtensa/translate.c
Log Message:
-----------
target/xtensa: reorganize register handling in translators
To support circular register dependencies in FLIX bundles opcode inputs
and outputs must be separate and adjustable. Circular dependencies can
be broken by making temporary copies of opcode inputs and substituting
them into the arguments array instead of the original registers.
E.g. the circular register dependency in the following bundle:
{ mov a2, a3 ; mov a3, a2 }
can be resolved by making copy a2' = a2 and substituting it as input
argument of the second opcode:
{ mov a2, a3 ; mov a3, a2' }
Change opcode translator prototype to accept OpcodeArg array as
argument. For each register argument initialize OpcodeArg::{in,out} with
TCGv_* of the respective register. Don't explicitly use cpu_R in the
opcode translators, use OpcodeArg::{in,out} instead.
Signed-off-by: Max Filippov <address@hidden>
Commit: 7aa783418707d5a1b1a38fa54b8d4f634e4843de
https://github.com/qemu/qemu/commit/7aa783418707d5a1b1a38fa54b8d4f634e4843de
Author: Max Filippov <address@hidden>
Date: 2019-02-28 (Thu, 28 Feb 2019)
Changed paths:
M target/xtensa/translate.c
Log Message:
-----------
target/xtensa: reorganize access to MAC16 registers
libisa represents MAC16 registers m0..m3 as an MR register file. Add
this register file and reference its registers directly from the
translate_mac16. Drop translator parameter that indicates whether opcode
argument is in ar or in mr.
Signed-off-by: Max Filippov <address@hidden>
Commit: 575e962a01ca502c7c2a8d671f83c5173446c68d
https://github.com/qemu/qemu/commit/575e962a01ca502c7c2a8d671f83c5173446c68d
Author: Max Filippov <address@hidden>
Date: 2019-02-28 (Thu, 28 Feb 2019)
Changed paths:
M target/xtensa/translate.c
Log Message:
-----------
target/xtensa: reorganize access to boolean registers
libisa represents boolean registers b0..b16 as a BR register file and as
BR4 and BR8 register groups. Add these register files and use
OpcodeArg::{in,out} parameters to access boolean registers in
translators.
Signed-off-by: Max Filippov <address@hidden>
Commit: 89bec9e9117d454d2101f7848475b11677ca99ff
https://github.com/qemu/qemu/commit/89bec9e9117d454d2101f7848475b11677ca99ff
Author: Max Filippov <address@hidden>
Date: 2019-02-28 (Thu, 28 Feb 2019)
Changed paths:
M target/xtensa/translate.c
Log Message:
-----------
target/xtensa: break circular register dependencies
Currently topologic opcode sorting stops at the first detected
dependency loop. Introduce struct opcode_arg_copy that describes
temporary register copy. Scan remaining opcodes searching for
dependencies that can be broken, break them by introducing temporary
register copies and record them in an array. In case of success
create local temporaries and initialize them with current register
values. Share single temporary copy between all register users. Delete
temporaries after translation.
Signed-off-by: Max Filippov <address@hidden>
Commit: 068e538a54552289a58689f21c99ed3696e59961
https://github.com/qemu/qemu/commit/068e538a54552289a58689f21c99ed3696e59961
Author: Max Filippov <address@hidden>
Date: 2019-02-28 (Thu, 28 Feb 2019)
Changed paths:
M target/xtensa/cpu.h
M target/xtensa/translate.c
Log Message:
-----------
target/xtensa: prioritize load/store in FLIX bundles
Load/store opcodes may raise MMU exceptions. Normally exceptions should
be checked in priority order before any actual operations, but since MMU
exceptions are tightly coupled with actual memory access, there's
currently no way to do it.
Approximate this behavior by executing all load, then all store, and
then all other opcodes in the FLIX bundles. Use opcode dependency
mechanism to express ordering. Mark load/store opcodes with
XTENSA_OP_{LOAD,STORE} flags. Newer libisa has classifier functions that
can tell whether opcode is a load or store, but this information is not
available in the existing overlays.
Signed-off-by: Max Filippov <address@hidden>
Commit: eb3f4298c96d79a5a67b904c28f293864cc5ccc3
https://github.com/qemu/qemu/commit/eb3f4298c96d79a5a67b904c28f293864cc5ccc3
Author: Max Filippov <address@hidden>
Date: 2019-02-28 (Thu, 28 Feb 2019)
Changed paths:
M target/xtensa/cpu.h
M target/xtensa/translate.c
Log Message:
-----------
target/xtensa: implement PREFCTL SR
Cache prefetch option adds an unprivileged SR PREFCTL. Add trivial
implementation for this SR.
Signed-off-by: Max Filippov <address@hidden>
Commit: 0ed040db363bd61bf70f9a464e98229095788bc4
https://github.com/qemu/qemu/commit/0ed040db363bd61bf70f9a464e98229095788bc4
Author: Max Filippov <address@hidden>
Date: 2019-02-28 (Thu, 28 Feb 2019)
Changed paths:
M tests/tcg/xtensa/macros.inc
Log Message:
-----------
tests/tcg/xtensa: indicate failed tests
When test suite with multiple tests fails it's not obvious which test
failed. Pring "failed" in every invocation of test_fail. Do printing
when DEBUG preprocessor macro is defined.
Signed-off-by: Max Filippov <address@hidden>
Commit: 906da882911415b493378ed1f8d7925d1871a02e
https://github.com/qemu/qemu/commit/906da882911415b493378ed1f8d7925d1871a02e
Author: Max Filippov <address@hidden>
Date: 2019-02-28 (Thu, 28 Feb 2019)
Changed paths:
M tests/tcg/xtensa/Makefile
M tests/tcg/xtensa/linker.ld.S
M tests/tcg/xtensa/vectors.S
Log Message:
-----------
tests/tcg/xtensa: support configurations w/o vecbase
Configurations w/o vecbase may have vectors not grouped together and not
in fixed order. They may not always be grouped into single output
sections by assigning next offset to dot, as it may sometimes move dot
backwards and sometimes they may even belong to different memory region.
Don't group vectors into single output section. Instead put each vector
into its own section ant put it at its default virtual address.
Reserve 4KBytes from the default vectors base and put rest of the code
and data starting from there. Mark vectors sections as executable,
otherwise their contents is discarded. There may be as little as 16
bytes reserved for some vectors, load handler address into a0 and use
ret.n to jump there to make vector code fit into this 16 byte space.
Signed-off-by: Max Filippov <address@hidden>
Commit: 306a69dad49e6efb6382371a7f4eaa627ef79fab
https://github.com/qemu/qemu/commit/306a69dad49e6efb6382371a7f4eaa627ef79fab
Author: Max Filippov <address@hidden>
Date: 2019-02-28 (Thu, 28 Feb 2019)
Changed paths:
M tests/tcg/xtensa/Makefile
Log Message:
-----------
tests/tcg/xtensa: support configs with LITBASE
Configurations with LITBASE register may use absolute literals by
default. Pass --no-absolute-literals option to assembler to use
PC-relative literals instead.
Signed-off-by: Max Filippov <address@hidden>
Commit: fafd5533430cc5c16f419282ae46874271b0d30c
https://github.com/qemu/qemu/commit/fafd5533430cc5c16f419282ae46874271b0d30c
Author: Max Filippov <address@hidden>
Date: 2019-02-28 (Thu, 28 Feb 2019)
Changed paths:
M tests/tcg/xtensa/macros.inc
Log Message:
-----------
tests/tcg/xtensa: don't use optional opcodes in generic code
Don't use 'loop' opcode in generic testsuite completion code, only use
core opcodes to make it work with any configuration.
Signed-off-by: Max Filippov <address@hidden>
Commit: 64eef9bf95a3d3759f2239f9e2b8425fc97858a7
https://github.com/qemu/qemu/commit/64eef9bf95a3d3759f2239f9e2b8425fc97858a7
Author: Max Filippov <address@hidden>
Date: 2019-02-28 (Thu, 28 Feb 2019)
Changed paths:
M tests/tcg/xtensa/test_b.S
Log Message:
-----------
tests/tcg/xtensa: fix endianness issues in test_b
Use bbci.l/bbsi.l instead of bbci/bbsi, as they are assembly macros that
accept little-endian bit number and produce correct immediate for both
little and big endian configurations. Choose value loaded into register
for bbc/bbs opcodes based on configuration endianness.
Signed-off-by: Max Filippov <address@hidden>
Commit: 912f161ff7bbb64c7d5b2eb6f81f830c80a6ef9b
https://github.com/qemu/qemu/commit/912f161ff7bbb64c7d5b2eb6f81f830c80a6ef9b
Author: Max Filippov <address@hidden>
Date: 2019-02-28 (Thu, 28 Feb 2019)
Changed paths:
M tests/tcg/xtensa/Makefile
M tests/tcg/xtensa/test_boolean.S
Log Message:
-----------
tests/tcg/xtensa: enable boolean tests
Uncomment test_boolean in the test makefile. Make actual tests code
conditional on the presence of boolean option in the config.
Signed-off-by: Max Filippov <address@hidden>
Commit: 66c58ba71b2ed49b5908ae4db146986d053e46be
https://github.com/qemu/qemu/commit/66c58ba71b2ed49b5908ae4db146986d053e46be
Author: Max Filippov <address@hidden>
Date: 2019-02-28 (Thu, 28 Feb 2019)
Changed paths:
M tests/tcg/xtensa/macros.inc
M tests/tcg/xtensa/test_break.S
Log Message:
-----------
tests/tcg/xtensa: conditionalize debug option tests
Make debug tests conditional on the presence of the debug option in the
config and tests that depend on the presence/number of instruction or
data breakpoint registers on the corresponding definitions. Use
configured debug interrupt level instead of the hardcoded value to set
up IRQ handler and access debug EPC register.
Signed-off-by: Max Filippov <address@hidden>
Commit: ecf5b577592be61b78b5d67724a1ebf559c9e695
https://github.com/qemu/qemu/commit/ecf5b577592be61b78b5d67724a1ebf559c9e695
Author: Max Filippov <address@hidden>
Date: 2019-02-28 (Thu, 28 Feb 2019)
Changed paths:
M tests/tcg/xtensa/test_cache.S
Log Message:
-----------
tests/tcg/xtensa: conditionalize cache option tests
Make data/instruction tests conditional on the presence of
data/instruction cache, whether they're lockable and whether data cache
is writeback.
Signed-off-by: Max Filippov <address@hidden>
Commit: 50f0171a9543f7a40abdbd36714fb1201cdc47b0
https://github.com/qemu/qemu/commit/50f0171a9543f7a40abdbd36714fb1201cdc47b0
Author: Max Filippov <address@hidden>
Date: 2019-02-28 (Thu, 28 Feb 2019)
Changed paths:
M tests/tcg/xtensa/test_clamps.S
M tests/tcg/xtensa/test_loop.S
M tests/tcg/xtensa/test_mac16.S
M tests/tcg/xtensa/test_max.S
M tests/tcg/xtensa/test_min.S
M tests/tcg/xtensa/test_mul16.S
M tests/tcg/xtensa/test_mul32.S
M tests/tcg/xtensa/test_nsa.S
M tests/tcg/xtensa/test_quo.S
M tests/tcg/xtensa/test_rem.S
M tests/tcg/xtensa/test_rst0.S
M tests/tcg/xtensa/test_sext.S
Log Message:
-----------
tests/tcg/xtensa: add straightforward conditionals
Make tests for optional instruction groups conditional on the presence
of corresponding options in the config.
Signed-off-by: Max Filippov <address@hidden>
Commit: 9c988226195c3d2b611352a76c0d8bd835ecb75b
https://github.com/qemu/qemu/commit/9c988226195c3d2b611352a76c0d8bd835ecb75b
Author: Max Filippov <address@hidden>
Date: 2019-02-28 (Thu, 28 Feb 2019)
Changed paths:
M tests/tcg/xtensa/macros.inc
M tests/tcg/xtensa/test_interrupt.S
Log Message:
-----------
tests/tcg/xtensa: conditionalize interrupt tests
Make interrupt tests conditional on the presence of interrupt option and
on the presence of level-1 and high level software interrupts. Don't use
hard-coded interrupt level for the high level interrupt tests, choose
high level software IRQ and use its configured level.
Signed-off-by: Max Filippov <address@hidden>
Commit: 02a5a4a8774b65ca619297bba4fe6e51bf9023d1
https://github.com/qemu/qemu/commit/02a5a4a8774b65ca619297bba4fe6e51bf9023d1
Author: Max Filippov <address@hidden>
Date: 2019-02-28 (Thu, 28 Feb 2019)
Changed paths:
M tests/tcg/xtensa/test_timer.S
Log Message:
-----------
tests/tcg/xtensa: conditionalize timer/CCOUNT tests
Make timer/CCOUNT tests conditional on the presence of timer option and
number of configured timers. Don't use hard coded interrupt levels for
timers, use configured values.
Signed-off-by: Max Filippov <address@hidden>
Commit: 50d3a0feaec5a88d5b3c1235fd058ff19f489885
https://github.com/qemu/qemu/commit/50d3a0feaec5a88d5b3c1235fd058ff19f489885
Author: Max Filippov <address@hidden>
Date: 2019-02-28 (Thu, 28 Feb 2019)
Changed paths:
M tests/tcg/xtensa/test_sr.S
Log Message:
-----------
tests/tcg/xtensa: conditionalize and expand SR tests
Make tests for specific special registers conditional on the presence of
the options that add these registers and test that the registers are not
accessible otherwise.
Signed-off-by: Max Filippov <address@hidden>
Commit: 9b2d08a066b85315fa41a3bbe8cc2186278c0f79
https://github.com/qemu/qemu/commit/9b2d08a066b85315fa41a3bbe8cc2186278c0f79
Author: Max Filippov <address@hidden>
Date: 2019-02-28 (Thu, 28 Feb 2019)
Changed paths:
M tests/tcg/xtensa/test_sr.S
Log Message:
-----------
tests/tcg/xtensa: fix SR tests for big endian configs
SR tests generate instructions that the assembler does not recognize and
thus must take care about configuration endianness.
Signed-off-by: Max Filippov <address@hidden>
Commit: 00988da4860c363522daa39709cb5985d6a6033a
https://github.com/qemu/qemu/commit/00988da4860c363522daa39709cb5985d6a6033a
Author: Max Filippov <address@hidden>
Date: 2019-02-28 (Thu, 28 Feb 2019)
Changed paths:
M tests/tcg/xtensa/test_s32c1i.S
Log Message:
-----------
tests/tcg/xtensa: conditionalize and fix s32c1i tests
Make s32c1i tests conditional on the presence of this option. Initialize
ATOMCTL SR when it's present to allow RCW transactions on uncached
memory.
Signed-off-by: Max Filippov <address@hidden>
Commit: c20e10eac83c1ec5c5c06f737bd06428fa55cbbc
https://github.com/qemu/qemu/commit/c20e10eac83c1ec5c5c06f737bd06428fa55cbbc
Author: Max Filippov <address@hidden>
Date: 2019-02-28 (Thu, 28 Feb 2019)
Changed paths:
M tests/tcg/xtensa/test_windowed.S
Log Message:
-----------
tests/tcg/xtensa: conditionalize windowed register tests
Make windowed register tests conditional on the presence of this option.
Fix tests to work correctly for both 32 and 64 physical registers.
Signed-off-by: Max Filippov <address@hidden>
Commit: 3db8a95e70be544af5969a54da5fad5ddc3090e1
https://github.com/qemu/qemu/commit/3db8a95e70be544af5969a54da5fad5ddc3090e1
Author: Max Filippov <address@hidden>
Date: 2019-02-28 (Thu, 28 Feb 2019)
Changed paths:
M tests/tcg/xtensa/test_mmu.S
M tests/tcg/xtensa/test_phys_mem.S
Log Message:
-----------
tests/tcg/xtensa: conditionalize MMU-related tests
Make MMU-related tests conditional on the presence of MMUv2 option.
Signed-off-by: Max Filippov <address@hidden>
Commit: ebbd775aab3a15b3d631e6a262353ece4575fcf5
https://github.com/qemu/qemu/commit/ebbd775aab3a15b3d631e6a262353ece4575fcf5
Author: Max Filippov <address@hidden>
Date: 2019-02-28 (Thu, 28 Feb 2019)
Changed paths:
M tests/tcg/xtensa/Makefile
A tests/tcg/xtensa/test_flix.S
Log Message:
-----------
tests/tcg/xtensa: add test for FLIX
Signed-off-by: Max Filippov <address@hidden>
Commit: 5e33b037b5153936c503b17f3e6b40fa34265268
https://github.com/qemu/qemu/commit/5e33b037b5153936c503b17f3e6b40fa34265268
Author: Max Filippov <address@hidden>
Date: 2019-02-28 (Thu, 28 Feb 2019)
Changed paths:
M tests/tcg/xtensa/Makefile
A tests/tcg/xtensa/test_lsc.S
Log Message:
-----------
tests/tcg/xtensa: add LSCI/LSCX group tests
Signed-off-by: Max Filippov <address@hidden>
Commit: 9d012e8ec2c75cf9d114e272cddbadcabd44f4f8
https://github.com/qemu/qemu/commit/9d012e8ec2c75cf9d114e272cddbadcabd44f4f8
Author: Max Filippov <address@hidden>
Date: 2019-02-28 (Thu, 28 Feb 2019)
Changed paths:
M tests/tcg/xtensa/Makefile
M tests/tcg/xtensa/macros.inc
A tests/tcg/xtensa/test_fp0_arith.S
Log Message:
-----------
tests/tcg/xtensa: add FP0 group arithmetic tests
Test arithmetic operations for normal, NaN and Inf arguments.
Signed-off-by: Max Filippov <address@hidden>
Commit: 710b15f0415e95110346b5cbed83e0ea58cc3657
https://github.com/qemu/qemu/commit/710b15f0415e95110346b5cbed83e0ea58cc3657
Author: Max Filippov <address@hidden>
Date: 2019-02-28 (Thu, 28 Feb 2019)
Changed paths:
M tests/tcg/xtensa/Makefile
A tests/tcg/xtensa/test_fp0_conv.S
Log Message:
-----------
tests/tcg/xtensa: add FP0 group conversion tests
Test conversions for normal, NaN and Inf arguments.
Signed-off-by: Max Filippov <address@hidden>
Commit: fd78bc55a44feecb385fa36cd149dbdc3110404b
https://github.com/qemu/qemu/commit/fd78bc55a44feecb385fa36cd149dbdc3110404b
Author: Max Filippov <address@hidden>
Date: 2019-02-28 (Thu, 28 Feb 2019)
Changed paths:
M tests/tcg/xtensa/Makefile
A tests/tcg/xtensa/test_fp1.S
Log Message:
-----------
tests/tcg/xtensa: add FP1 group tests
Test comparisons and conditional move operations.
Signed-off-by: Max Filippov <address@hidden>
Commit: de0cebd93089ff2ebf2ebf9d287381eb73cbb9aa
https://github.com/qemu/qemu/commit/de0cebd93089ff2ebf2ebf9d287381eb73cbb9aa
Author: Max Filippov <address@hidden>
Date: 2019-02-28 (Thu, 28 Feb 2019)
Changed paths:
M tests/tcg/xtensa/Makefile
A tests/tcg/xtensa/test_fp_cpenable.S
Log Message:
-----------
tests/tcg/xtensa: add FPU2000 coprocessor tests
Signed-off-by: Max Filippov <address@hidden>
Commit: 4179575898fcc17c5e67306a357b8dfe64122e8e
https://github.com/qemu/qemu/commit/4179575898fcc17c5e67306a357b8dfe64122e8e
Author: Peter Maydell <address@hidden>
Date: 2019-02-28 (Thu, 28 Feb 2019)
Changed paths:
M target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c
M target/xtensa/cpu.h
M target/xtensa/helper.c
M target/xtensa/helper.h
M target/xtensa/import_core.sh
M target/xtensa/overlay_tool.h
M target/xtensa/translate.c
M target/xtensa/win_helper.c
M tests/tcg/xtensa/Makefile
M tests/tcg/xtensa/linker.ld.S
M tests/tcg/xtensa/macros.inc
M tests/tcg/xtensa/test_b.S
M tests/tcg/xtensa/test_boolean.S
M tests/tcg/xtensa/test_break.S
M tests/tcg/xtensa/test_cache.S
M tests/tcg/xtensa/test_clamps.S
A tests/tcg/xtensa/test_flix.S
A tests/tcg/xtensa/test_fp0_arith.S
A tests/tcg/xtensa/test_fp0_conv.S
A tests/tcg/xtensa/test_fp1.S
A tests/tcg/xtensa/test_fp_cpenable.S
M tests/tcg/xtensa/test_interrupt.S
M tests/tcg/xtensa/test_loop.S
A tests/tcg/xtensa/test_lsc.S
M tests/tcg/xtensa/test_mac16.S
M tests/tcg/xtensa/test_max.S
M tests/tcg/xtensa/test_min.S
M tests/tcg/xtensa/test_mmu.S
M tests/tcg/xtensa/test_mul16.S
M tests/tcg/xtensa/test_mul32.S
M tests/tcg/xtensa/test_nsa.S
M tests/tcg/xtensa/test_phys_mem.S
M tests/tcg/xtensa/test_quo.S
M tests/tcg/xtensa/test_rem.S
M tests/tcg/xtensa/test_rst0.S
M tests/tcg/xtensa/test_s32c1i.S
M tests/tcg/xtensa/test_sext.S
M tests/tcg/xtensa/test_sr.S
M tests/tcg/xtensa/test_timer.S
M tests/tcg/xtensa/test_windowed.S
M tests/tcg/xtensa/vectors.S
Log Message:
-----------
Merge remote-tracking branch 'remotes/xtensa/tags/20190228-xtensa' into
staging
target/xtensa: FLIX support, various fixes and test improvements
- add FLIX (flexible length instructions extension) support;
- make testsuite runnable on wider range of xtensa cores;
- add floating point opcode tests;
- don't add duplicate 'static' in import_core.sh script;
- fix undefined opcodes detection in test_mmuhifi_c3 overlay.
# gpg: Signature made Thu 28 Feb 2019 12:53:23 GMT
# gpg: using RSA key 2B67854B98E5327DCDEB17D851F9CC91F83FA044
# gpg: issuer "address@hidden"
# gpg: Good signature from "Max Filippov <address@hidden>" [unknown]
# gpg: aka "Max Filippov <address@hidden>" [full]
# gpg: aka "Max Filippov <address@hidden>" [full]
# Primary key fingerprint: 2B67 854B 98E5 327D CDEB 17D8 51F9 CC91 F83F A044
* remotes/xtensa/tags/20190228-xtensa: (40 commits)
tests/tcg/xtensa: add FPU2000 coprocessor tests
tests/tcg/xtensa: add FP1 group tests
tests/tcg/xtensa: add FP0 group conversion tests
tests/tcg/xtensa: add FP0 group arithmetic tests
tests/tcg/xtensa: add LSCI/LSCX group tests
tests/tcg/xtensa: add test for FLIX
tests/tcg/xtensa: conditionalize MMU-related tests
tests/tcg/xtensa: conditionalize windowed register tests
tests/tcg/xtensa: conditionalize and fix s32c1i tests
tests/tcg/xtensa: fix SR tests for big endian configs
tests/tcg/xtensa: conditionalize and expand SR tests
tests/tcg/xtensa: conditionalize timer/CCOUNT tests
tests/tcg/xtensa: conditionalize interrupt tests
tests/tcg/xtensa: add straightforward conditionals
tests/tcg/xtensa: conditionalize cache option tests
tests/tcg/xtensa: conditionalize debug option tests
tests/tcg/xtensa: enable boolean tests
tests/tcg/xtensa: fix endianness issues in test_b
tests/tcg/xtensa: don't use optional opcodes in generic code
tests/tcg/xtensa: support configs with LITBASE
...
Signed-off-by: Peter Maydell <address@hidden>
Compare: https://github.com/qemu/qemu/compare/9403bccfe3e2...4179575898fc
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