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[Qemu-commits] [qemu/qemu] 7c3db4: hw/arm/virt: Set VIRT_COMPAT_3_0 comp

From: GitHub
Subject: [Qemu-commits] [qemu/qemu] 7c3db4: hw/arm/virt: Set VIRT_COMPAT_3_0 compat
Date: Fri, 02 Nov 2018 11:22:01 -0700 
  Branch: refs/heads/master
  Home:   https://github.com/qemu/qemu
  Commit: 7c3db4fdd29bb1d660b0ff4da02664e7ecafaaed
      
https://github.com/qemu/qemu/commit/7c3db4fdd29bb1d660b0ff4da02664e7ecafaaed
  Author: Eric Auger <address@hidden>
  Date:   2018-11-02 (Fri, 02 Nov 2018)

  Changed paths:
    M hw/arm/virt.c

  Log Message:
  -----------
  hw/arm/virt: Set VIRT_COMPAT_3_0 compat

We are missing the VIRT_COMPAT_3_0 definition and setting.
Let's add them.

Signed-off-by: Eric Auger <address@hidden>
Reviewed-by: Andrew Jones <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 19790847e25c7e82bba9eb13d82894506eeabe09
      
https://github.com/qemu/qemu/commit/19790847e25c7e82bba9eb13d82894506eeabe09
  Author: Julia Suvorova <address@hidden>
  Date:   2018-11-02 (Fri, 02 Nov 2018)

  Changed paths:
    M hw/char/Makefile.objs
    A hw/char/nrf51_uart.c
    M hw/char/trace-events
    A include/hw/char/nrf51_uart.h

  Log Message:
  -----------
  hw/char: Implement nRF51 SoC UART

Not implemented: CTS/NCTS, PSEL*.

Signed-off-by: Julia Suvorova <address@hidden>
Reviewed-by: Stefan Hajnoczi <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>


  Commit: b0014913f2e415abe3434dec7ad7ce20afb491cd
      
https://github.com/qemu/qemu/commit/b0014913f2e415abe3434dec7ad7ce20afb491cd
  Author: Julia Suvorova <address@hidden>
  Date:   2018-11-02 (Fri, 02 Nov 2018)

  Changed paths:
    M hw/arm/microbit.c
    M hw/arm/nrf51_soc.c
    M include/hw/arm/nrf51_soc.h

  Log Message:
  -----------
  hw/arm/nrf51_soc: Connect UART to nRF51 SoC

Wire up nRF51 UART in the corresponding SoC.

Signed-off-by: Julia Suvorova <address@hidden>
Reviewed-by: Stefan Hajnoczi <address@hidden>
Reviewed-by: Alistair Francis <address@hidden>
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>


  Commit: a2c9a356f5492b0b8ba3bfcef7ac7f6c33f379d3
      
https://github.com/qemu/qemu/commit/a2c9a356f5492b0b8ba3bfcef7ac7f6c33f379d3
  Author: Julia Suvorova <address@hidden>
  Date:   2018-11-02 (Fri, 02 Nov 2018)

  Changed paths:
    M tests/boot-serial-test.c

  Log Message:
  -----------
  tests/boot-serial-test: Add microbit board testcase

New mini-kernel test for nRF51 SoC UART.

Signed-off-by: Julia Suvorova <address@hidden>
Acked-by: Thomas Huth <address@hidden>
Reviewed-by: Stefan Hajnoczi <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 22461bd2e59380c08683044c580c18b1f3c9ce26
      
https://github.com/qemu/qemu/commit/22461bd2e59380c08683044c580c18b1f3c9ce26
  Author: Philippe Mathieu-Daudé <address@hidden>
  Date:   2018-11-02 (Fri, 02 Nov 2018)

  Changed paths:
    M MAINTAINERS

  Log Message:
  -----------
  MAINTAINERS: Remove bouncing email in ARM ACPI

Shannon Zhao's email at Huawei is bouncing: remove it.

    X-Failed-Recipients: address@hidden
    ** Address not found **
    Your message wasn't delivered to address@hidden because the address 
couldn't be found, or is unable to receive mail.

Note that the section still contains his personal email (see e59f13d76bb).

Signed-off-by: Philippe Mathieu-Daudé <address@hidden>
Acked-by: Shannon Zhao <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 9a93b2fa0ed8de66a9deb9106ce5ddc2a65d68f0
      
https://github.com/qemu/qemu/commit/9a93b2fa0ed8de66a9deb9106ce5ddc2a65d68f0
  Author: Prasad J Pandit <address@hidden>
  Date:   2018-11-02 (Fri, 02 Nov 2018)

  Changed paths:
    M hw/arm/strongarm.c

  Log Message:
  -----------
  strongarm: mask off high[31:28] bits from dir and state registers

The high[31:28] bits of 'direction' and 'state' registers of
SA-1100/SA-1110 device are reserved. Setting them may lead to
OOB 's->handler[]' array access issue. Mask off [31:28] bits to
avoid it.

Reported-by: Moguofang <address@hidden>
Signed-off-by: Prasad J Pandit <address@hidden>
Message-id: address@hidden
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 5e9fcbd7df8cdddab6566a764cf4e2d4a491fa02
      
https://github.com/qemu/qemu/commit/5e9fcbd7df8cdddab6566a764cf4e2d4a491fa02
  Author: Philippe Mathieu-Daudé <address@hidden>
  Date:   2018-11-02 (Fri, 02 Nov 2018)

  Changed paths:
    M hw/arm/xilinx_zynq.c

  Log Message:
  -----------
  hw/arm/xilinx_zynq: Use the ARRAY_SIZE macro

Signed-off-by: Philippe Mathieu-Daudé <address@hidden>
Reviewed-by: Alistair Francis <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 0f8d06f16c9d1041d728d09d464462ebe713c662
      
https://github.com/qemu/qemu/commit/0f8d06f16c9d1041d728d09d464462ebe713c662
  Author: Richard Henderson <address@hidden>
  Date:   2018-11-02 (Fri, 02 Nov 2018)

  Changed paths:
    M target/arm/cpu.c
    M target/arm/cpu.h

  Log Message:
  -----------
  target/arm: Conditionalize some asserts on aarch32 support

When populating id registers from kvm, on a host that doesn't support
aarch32 mode at all, neither arm_div nor jazelle will be supported either.

Signed-off-by: Richard Henderson <address@hidden>
Reviewed-by: Alex Bennée <address@hidden>
Tested-by: Alex Bennée <address@hidden>
Message-id: address@hidden
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>


  Commit: b89de436ff63218d31122b2176f7785b0628b3c6
      
https://github.com/qemu/qemu/commit/b89de436ff63218d31122b2176f7785b0628b3c6
  Author: Edgar E. Iglesias <address@hidden>
  Date:   2018-11-02 (Fri, 02 Nov 2018)

  Changed paths:
    M default-configs/aarch64-softmmu.mak
    M hw/arm/Makefile.objs
    A hw/arm/xlnx-versal.c
    A include/hw/arm/xlnx-versal.h

  Log Message:
  -----------
  hw/arm: versal: Add a model of Xilinx Versal SoC

Add a model of Xilinx Versal SoC.

Signed-off-by: Edgar E. Iglesias <address@hidden>
Message-id: address@hidden
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 6f16da53ffe4567c0353f85055df04860eb4e6fc
      
https://github.com/qemu/qemu/commit/6f16da53ffe4567c0353f85055df04860eb4e6fc
  Author: Edgar E. Iglesias <address@hidden>
  Date:   2018-11-02 (Fri, 02 Nov 2018)

  Changed paths:
    M hw/arm/Makefile.objs
    A hw/arm/xlnx-versal-virt.c

  Log Message:
  -----------
  hw/arm: versal: Add a virtual Xilinx Versal board

Add a virtual Xilinx Versal board.

This board is based on the Xilinx Versal SoC. The exact
details of what peripherals are attached to this board
will remain in control of QEMU. QEMU will generate an
FDT on the fly for Linux and other software to auto-discover
peripherals.

Signed-off-by: Edgar E. Iglesias <address@hidden>
Message-id: address@hidden
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 7d56239f159afc2e7bd42623947e56ba48f37836
      
https://github.com/qemu/qemu/commit/7d56239f159afc2e7bd42623947e56ba48f37836
  Author: Peter Maydell <address@hidden>
  Date:   2018-11-02 (Fri, 02 Nov 2018)

  Changed paths:
    M MAINTAINERS
    M default-configs/aarch64-softmmu.mak
    M hw/arm/Makefile.objs
    M hw/arm/microbit.c
    M hw/arm/nrf51_soc.c
    M hw/arm/strongarm.c
    M hw/arm/virt.c
    M hw/arm/xilinx_zynq.c
    A hw/arm/xlnx-versal-virt.c
    A hw/arm/xlnx-versal.c
    M hw/char/Makefile.objs
    A hw/char/nrf51_uart.c
    M hw/char/trace-events
    M include/hw/arm/nrf51_soc.h
    A include/hw/arm/xlnx-versal.h
    A include/hw/char/nrf51_uart.h
    M target/arm/cpu.c
    M target/arm/cpu.h
    M tests/boot-serial-test.c

  Log Message:
  -----------
  Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20181102' 
into staging

target-arm queue:
 * microbit: Add the UART to our nRF51 SoC model
 * Add a virtual Xilinx Versal board "xlnx-versal-virt"
 * hw/arm/virt: Set VIRT_COMPAT_3_0 compat
 * MAINTAINERS: Remove bouncing email in ARM ACPI
 * strongarm: mask off high[31:28] bits from dir and state registers
 * target/arm: Conditionalize some asserts on aarch32 support
 * hw/arm/xilinx_zynq: Use the ARRAY_SIZE macro

# gpg: Signature made Fri 02 Nov 2018 17:14:43 GMT
# gpg:                using RSA key 3C2525ED14360CDE
# gpg: Good signature from "Peter Maydell <address@hidden>"
# gpg:                 aka "Peter Maydell <address@hidden>"
# gpg:                 aka "Peter Maydell <address@hidden>"
# Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83  15CF 3C25 25ED 1436 0CDE

* remotes/pmaydell/tags/pull-target-arm-20181102:
  hw/arm: versal: Add a virtual Xilinx Versal board
  hw/arm: versal: Add a model of Xilinx Versal SoC
  target/arm: Conditionalize some asserts on aarch32 support
  hw/arm/xilinx_zynq: Use the ARRAY_SIZE macro
  strongarm: mask off high[31:28] bits from dir and state registers
  MAINTAINERS: Remove bouncing email in ARM ACPI
  tests/boot-serial-test: Add microbit board testcase
  hw/arm/nrf51_soc: Connect UART to nRF51 SoC
  hw/char: Implement nRF51 SoC UART
  hw/arm/virt: Set VIRT_COMPAT_3_0 compat

Signed-off-by: Peter Maydell <address@hidden>


Compare: https://github.com/qemu/qemu/compare/69e2d0384341...7d56239f159a
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