[Qemu-commits] [qemu/qemu] d41989: hw/intc/arm_gicv3: fix an extra left-shift when re...

[GitHub]

  Branch: refs/heads/master
  Home:   https://github.com/qemu/qemu
  Commit: d419890c0448281d0cf11d9384d9a30c8808f648
      
https://github.com/qemu/qemu/commit/d419890c0448281d0cf11d9384d9a30c8808f648
  Author: Amol Surati <address@hidden>
  Date:   2018-06-22 (Fri, 22 Jun 2018)

  Changed paths:
    M hw/intc/arm_gicv3_dist.c
    M hw/intc/arm_gicv3_redist.c

  Log Message:
  -----------
  hw/intc/arm_gicv3: fix an extra left-shift when reading IPRIORITYR

When either GICD_IPRIORITYR or GICR_IPRIORITYR is read as a 32-bit
register, the post left-shift operator in the for loop causes an
extra shift after the least significant byte has been placed.

The 32-bit value actually returned is therefore the expected value
shifted left by 8 bits.

Signed-off-by: Amol Surati <address@hidden>
Message-id: address@hidden
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 8297cb13e407db8a96cc7ed6b6a6c318a150759a
      
https://github.com/qemu/qemu/commit/8297cb13e407db8a96cc7ed6b6a6c318a150759a
  Author: Julia Suvorova <address@hidden>
  Date:   2018-06-22 (Fri, 22 Jun 2018)

  Changed paths:
    M target/arm/translate.c

  Log Message:
  -----------
  target/arm: Minor cleanup for ARMv6-M 32-bit instructions

The arrays were made static, "if" was simplified because V7M and V8M
define V6 feature.

Signed-off-by: Julia Suvorova <address@hidden>
Reviewed-by: Stefan Hajnoczi <address@hidden>
Message-id: address@hidden
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 5ff9aaabdc6aec367ba139bf3f2ccacd918a495f
      
https://github.com/qemu/qemu/commit/5ff9aaabdc6aec367ba139bf3f2ccacd918a495f
  Author: Zheng Xiang <address@hidden>
  Date:   2018-06-22 (Fri, 22 Jun 2018)

  Changed paths:
    M target/arm/kvm.c

  Log Message:
  -----------
  target-arm: fix a segmentation fault due to illegal memory access

The elements of kvm_devices_head list are freed in kvm_arm_machine_init_done(),
but we still access these illegal memory in kvm_arm_devlistener_del().

This will cause segment fault when booting guest with MALLOC_PERTURB_=1.

Signed-off-by: Zheng Xiang <address@hidden>
Message-id: address@hidden
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 77d361b13c19fdf881bff044a5bec99108cf2da2
      
https://github.com/qemu/qemu/commit/77d361b13c19fdf881bff044a5bec99108cf2da2
  Author: Eric Auger <address@hidden>
  Date:   2018-06-22 (Fri, 22 Jun 2018)

  Changed paths:
    M include/standard-headers/linux/pci_regs.h
    M include/standard-headers/linux/virtio_gpu.h
    M include/standard-headers/linux/virtio_net.h
    M linux-headers/LICENSES/exceptions/Linux-syscall-note
    M linux-headers/LICENSES/preferred/GPL-2.0
    M linux-headers/asm-arm/kvm.h
    M linux-headers/asm-arm/unistd-common.h
    M linux-headers/asm-arm64/kvm.h
    M linux-headers/asm-generic/unistd.h
    M linux-headers/asm-powerpc/unistd.h
    M linux-headers/asm-x86/unistd_32.h
    M linux-headers/asm-x86/unistd_64.h
    M linux-headers/asm-x86/unistd_x32.h
    M linux-headers/linux/kvm.h
    M linux-headers/linux/psp-sev.h

  Log Message:
  -----------
  linux-headers: Update to kernel mainline commit b357bf602

Update our kernel headers to mainline commit
b357bf6023a948cf6a9472f07a1b0caac0e4f8e8
("Merge tag 'for-linus' of git://git.kernel.org/pub/scm/virt/kvm/kvm")

Signed-off-by: Eric Auger <address@hidden>
Message-id: address@hidden
[PMM:  clarified commit message]
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 19d1bd0b586a537805c6fe3b590f4ca8ec7a4912
      
https://github.com/qemu/qemu/commit/19d1bd0b586a537805c6fe3b590f4ca8ec7a4912
  Author: Eric Auger <address@hidden>
  Date:   2018-06-22 (Fri, 22 Jun 2018)

  Changed paths:
    M hw/intc/arm_gic_kvm.c
    M hw/intc/arm_gicv3_its_kvm.c
    M hw/intc/arm_gicv3_kvm.c
    M target/arm/kvm.c
    M target/arm/kvm_arm.h

  Log Message:
  -----------
  target/arm: Allow KVM device address overwriting

for KVM_VGIC_V3_ADDR_TYPE_REDIST_REGION attribute, the attribute
data pointed to by kvm_device_attr.addr is a OR of the
redistributor region address and other fields such as the index
of the redistributor region and the number of redistributors the
region can contain.

The existing machine init done notifier framework sets the address
field to the actual address of the device and does not allow to OR
this value with other fields.

This patch extends the KVMDevice struct with a new kda_addr_ormask
member. Its value is passed at registration time and OR'ed with the
resolved address on kvm_arm_set_device_addr().

Signed-off-by: Eric Auger <address@hidden>
Reviewed-by: Peter Maydell <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 1e575b66643a4311b9a6cbf0744f7f5aeba5e181
      
https://github.com/qemu/qemu/commit/1e575b66643a4311b9a6cbf0744f7f5aeba5e181
  Author: Eric Auger <address@hidden>
  Date:   2018-06-22 (Fri, 22 Jun 2018)

  Changed paths:
    M hw/arm/virt.c
    M hw/intc/arm_gicv3.c
    M hw/intc/arm_gicv3_common.c
    M hw/intc/arm_gicv3_kvm.c
    M include/hw/intc/arm_gicv3_common.h

  Log Message:
  -----------
  hw/intc/arm_gicv3: Introduce redist-region-count array property

To prepare for multiple redistributor regions, we introduce
an array of uint32_t properties that stores the redistributor
count of each redistributor region.

Non accelerated VGICv3 only supports a single redistributor region.
The capacity of all redist regions is checked against the number of
vcpus.

Machvirt is updated to set those properties, ie. a single
redistributor region with count set to the number of vcpus
capped by 123.

Signed-off-by: Eric Auger <address@hidden>
Reviewed-by: Andrew Jones <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 80d673338959c813770bd5b903e3061db58b1999
      
https://github.com/qemu/qemu/commit/80d673338959c813770bd5b903e3061db58b1999
  Author: Eric Auger <address@hidden>
  Date:   2018-06-22 (Fri, 22 Jun 2018)

  Changed paths:
    M hw/intc/arm_gicv3_kvm.c

  Log Message:
  -----------
  hw/intc/arm_gicv3_kvm: Get prepared to handle multiple redist regions

Let's check if KVM_VGIC_V3_ADDR_TYPE_REDIST_REGION is supported.
If not, we check the number of redist region is equal to 1 and use the
legacy KVM_VGIC_V3_ADDR_TYPE_REDIST attribute. Otherwise we use
the new attribute and allow to register multiple regions to the
KVM device.

Signed-off-by: Eric Auger <address@hidden>
Reviewed-by: Peter Maydell <address@hidden>
Reviewed-by: Andrew Jones <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: f90747c4e8fb689a8cea9c104ed6c13bd8e5086d
      
https://github.com/qemu/qemu/commit/f90747c4e8fb689a8cea9c104ed6c13bd8e5086d
  Author: Eric Auger <address@hidden>
  Date:   2018-06-22 (Fri, 22 Jun 2018)

  Changed paths:
    M hw/arm/virt.c
    M include/hw/arm/virt.h

  Log Message:
  -----------
  hw/arm/virt: GICv3 DT node with one or two redistributor regions

This patch allows the creation of a GICv3 node with 1 or 2
redistributor regions depending on the number of smu_cpus.
The second redistributor region is located just after the
existing RAM region, at 256GB and contains up to up to 512 vcpus.

Please refer to kernel documentation for further node details:
Documentation/devicetree/bindings/interrupt-controller/arm,gic-v3.txt

Signed-off-by: Eric Auger <address@hidden>
Reviewed-by: Andrew Jones <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: a1de312f5690a1a4f3ff37319045f6ec7bdfcd31
      
https://github.com/qemu/qemu/commit/a1de312f5690a1a4f3ff37319045f6ec7bdfcd31
  Author: Eric Auger <address@hidden>
  Date:   2018-06-22 (Fri, 22 Jun 2018)

  Changed paths:
    M hw/arm/virt-acpi-build.c

  Log Message:
  -----------
  hw/arm/virt-acpi-build: Advertise one or two GICR structures

Depending on the number of smp_cpus we now register one or two
GICR structures.

Signed-off-by: Eric Auger <address@hidden>
Reviewed-by: Andrew Jones <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 03d72fa13cef2454aeaedea387a2e505c77481b4
      
https://github.com/qemu/qemu/commit/03d72fa13cef2454aeaedea387a2e505c77481b4
  Author: Eric Auger <address@hidden>
  Date:   2018-06-22 (Fri, 22 Jun 2018)

  Changed paths:
    M hw/arm/virt.c

  Log Message:
  -----------
  hw/arm/virt: Register two redistributor regions when necessary

With a VGICv3 KVM device, if the number of vcpus exceeds the
capacity of the legacy redistributor region (123 redistributors),
we now attempt to register a second redistributor region. Up to
512 redistributors can fit in this latter on top of the 123 allowed
by the legacy redistributor region.

Registering this second redistributor region is possible if the
host kernel supports the following VGICv3 KVM device group/attribute:
KVM_DEV_ARM_VGIC_GRP_ADDR/KVM_VGIC_V3_ADDR_TYPE_REDIST_REGION.

In case the host kernel does not support the registration of several
redistributor regions and the requested number of vcpus exceeds the
capacity of the legacy redistributor region, the GICv3 device
initialization fails with a proper error message and qemu exits.

At the moment the max number of vcpus still is capped by the
virt machine class max_cpus.

Signed-off-by: Eric Auger <address@hidden>
Reviewed-by: Andrew Jones <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 601d626d148a6e50b4a0b5ae38f98682c5bf5e2a
      
https://github.com/qemu/qemu/commit/601d626d148a6e50b4a0b5ae38f98682c5bf5e2a
  Author: Eric Auger <address@hidden>
  Date:   2018-06-22 (Fri, 22 Jun 2018)

  Changed paths:
    M hw/arm/virt-acpi-build.c
    M hw/arm/virt.c
    M include/hw/arm/virt.h

  Log Message:
  -----------
  hw/arm/virt: Add a new 256MB ECAM region

This patch defines a new ECAM region located after the 256GB limit.

The virt machine state is augmented with a new highmem_ecam field
which guards the usage of this new ECAM region instead of the legacy
16MB one. With the highmem ECAM region, up to 256 PCIe buses can be
used.

Signed-off-by: Eric Auger <address@hidden>
Reviewed-by: Laszlo Ersek <address@hidden>
Reviewed-by: Andrew Jones <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 8ae9a1ca5b9bb0b3be06d51914ffba7c20dd62f8
      
https://github.com/qemu/qemu/commit/8ae9a1ca5b9bb0b3be06d51914ffba7c20dd62f8
  Author: Eric Auger <address@hidden>
  Date:   2018-06-22 (Fri, 22 Jun 2018)

  Changed paths:
    M hw/arm/virt.c

  Log Message:
  -----------
  hw/arm/virt: Add virt-3.0 machine type

Add virt-3.0 machine type.

Signed-off-by: Eric Auger <address@hidden>
Reviewed-by: Laszlo Ersek <address@hidden>
Reviewed-by: Andrew Jones <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 17ec075a651a3f9613429c2d97018fce459ed943
      
https://github.com/qemu/qemu/commit/17ec075a651a3f9613429c2d97018fce459ed943
  Author: Eric Auger <address@hidden>
  Date:   2018-06-22 (Fri, 22 Jun 2018)

  Changed paths:
    M hw/arm/virt.c
    M include/hw/arm/virt.h

  Log Message:
  -----------
  hw/arm/virt: Use 256MB ECAM region by default

With this patch, virt-3.0 machine uses a new 256MB ECAM region
by default instead of the legacy 16MB one, if highmem is set
(LPAE supported by the guest) and (!firmware_loaded || aarch64).

Indeed aarch32 mode FW may not support this high ECAM region.

Signed-off-by: Eric Auger <address@hidden>
Reviewed-by: Laszlo Ersek <address@hidden>
Reviewed-by: Andrew Jones <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: b10fbd5363e58a9996ad9af0f8f456d89770b0a9
      
https://github.com/qemu/qemu/commit/b10fbd5363e58a9996ad9af0f8f456d89770b0a9
  Author: Eric Auger <address@hidden>
  Date:   2018-06-22 (Fri, 22 Jun 2018)

  Changed paths:
    M hw/arm/virt.c

  Log Message:
  -----------
  hw/arm/virt: Increase max_cpus to 512

virt 3.0 now allows up to 512 vcpus whereas for earlier machine
types, max_cpus was set to 255 and any attempt to start the
machine with vcpus > 255 was rejected at a very early stage,
in vl.c/main level.

512 is the max supported by KVM. Anyway the actual vcpu count
that can be achieved depends on other parameters such as the
acceleration mode, the vgic version, the host kernel version.
Those are discovered later on.

Signed-off-by: Eric Auger <address@hidden>
Reviewed-by: Andrew Jones <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: ebac5458c7517ed7b8ee06eb90beacc7472b295d
      
https://github.com/qemu/qemu/commit/ebac5458c7517ed7b8ee06eb90beacc7472b295d
  Author: Edgar E. Iglesias <address@hidden>
  Date:   2018-06-22 (Fri, 22 Jun 2018)

  Changed paths:
    M target/arm/cpu.c

  Log Message:
  -----------
  target-arm: Add the Cortex-R5F

Add the Cortex-R5F with the optional FPU enabled.

Reviewed-by: KONRAD Frederic <address@hidden>
Reviewed-by: Alistair Francis <address@hidden>
Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
Tested-by: Philippe Mathieu-Daudé <address@hidden>
Signed-off-by: Edgar E. Iglesias <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: eb24d4d38e0e177b2ef8189a9930eeca9277f097
      
https://github.com/qemu/qemu/commit/eb24d4d38e0e177b2ef8189a9930eeca9277f097
  Author: Edgar E. Iglesias <address@hidden>
  Date:   2018-06-22 (Fri, 22 Jun 2018)

  Changed paths:
    M hw/arm/xlnx-zcu102.c
    M hw/arm/xlnx-zynqmp.c

  Log Message:
  -----------
  xlnx-zynqmp: Swap Cortex-R5 for Cortex-R5F

The ZynqMP has Cortex-R5Fs with the optional FPU enabled.

Reviewed-by: KONRAD Frederic <address@hidden>
Reviewed-by: Alistair Francis <address@hidden>
Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
Tested-by: Philippe Mathieu-Daudé <address@hidden>
Signed-off-by: Edgar E. Iglesias <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 344f4b1581f3d629954a1623736677827a0af750
      
https://github.com/qemu/qemu/commit/344f4b1581f3d629954a1623736677827a0af750
  Author: Peter Maydell <address@hidden>
  Date:   2018-06-22 (Fri, 22 Jun 2018)

  Changed paths:
    M MAINTAINERS
    M default-configs/arm-softmmu.mak
    M hw/misc/Makefile.objs
    M hw/misc/trace-events
    A hw/misc/tz-mpc.c
    A include/hw/misc/tz-mpc.h

  Log Message:
  -----------
  hw/misc/tz-mpc.c: Implement the Arm TrustZone Memory Protection Controller

Implement the Arm TrustZone Memory Protection Controller, which sits
in front of RAM and allows secure software to configure it to either
pass through or reject transactions.

We implement the MPC as a QEMU IOMMU, which will direct transactions
either through to the devices and memory behind it or to a special
"never works" AddressSpace if they are blocked.

This initial commit implements the skeleton of the device:
 * it always permits accesses
 * it doesn't implement most of the registers
 * it doesn't implement the interrupt or other behaviour
   for blocked transactions

Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Alex Bennée <address@hidden>
Reviewed-by: Eric Auger <address@hidden>
Message-id: address@hidden


  Commit: cdb6099818a78e80b307432f6f9c143452135c59
      
https://github.com/qemu/qemu/commit/cdb6099818a78e80b307432f6f9c143452135c59
  Author: Peter Maydell <address@hidden>
  Date:   2018-06-22 (Fri, 22 Jun 2018)

  Changed paths:
    M hw/misc/tz-mpc.c
    M include/hw/misc/tz-mpc.h

  Log Message:
  -----------
  hw/misc/tz-mpc.c: Implement registers

Implement the missing registers for the TZ MPC.

Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Eric Auger <address@hidden>
Message-id: address@hidden


  Commit: 57c49a6e8773bcce0d407ff4d9b2de7a904f1b0d
      
https://github.com/qemu/qemu/commit/57c49a6e8773bcce0d407ff4d9b2de7a904f1b0d
  Author: Peter Maydell <address@hidden>
  Date:   2018-06-22 (Fri, 22 Jun 2018)

  Changed paths:
    M hw/misc/tz-mpc.c

  Log Message:
  -----------
  hw/misc/tz-mpc.c: Implement correct blocked-access behaviour

The MPC is guest-configurable for whether blocked accesses:
 * should be RAZ/WI or cause a bus error
 * should generate an interrupt or not

Implement this behaviour in the blocked-access handlers.

Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Eric Auger <address@hidden>
Message-id: address@hidden


  Commit: dd29d0687d472be0c92b554383d2d8549fe37584
      
https://github.com/qemu/qemu/commit/dd29d0687d472be0c92b554383d2d8549fe37584
  Author: Peter Maydell <address@hidden>
  Date:   2018-06-22 (Fri, 22 Jun 2018)

  Changed paths:
    M hw/misc/trace-events
    M hw/misc/tz-mpc.c

  Log Message:
  -----------
  hw/misc/tz_mpc.c: Honour the BLK_LUT settings in translate

The final part of the Memory Protection Controller we need to
implement is actually using the BLK_LUT data programmed by the
guest to determine whether to block the transaction or not.

Since this means we now change transaction mappings when
the guest writes to BLK_LUT, we must also call the IOMMU
notifiers at that point.

Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Eric Auger <address@hidden>
Message-id: address@hidden


  Commit: 3fd3cb2f6f1b3ada95a728e2bf0a0cfa4c84a8e1
      
https://github.com/qemu/qemu/commit/3fd3cb2f6f1b3ada95a728e2bf0a0cfa4c84a8e1
  Author: Peter Maydell <address@hidden>
  Date:   2018-06-22 (Fri, 22 Jun 2018)

  Changed paths:
    M hw/misc/iotkit-secctl.c
    M include/hw/misc/iotkit-secctl.h

  Log Message:
  -----------
  hw/misc/iotkit-secctl.c: Implement SECMPCINTSTATUS

Implement the SECMPCINTSTATUS register. This is the only register
in the security controller that deals with Memory Protection
Controllers, and it simply provides a read-only view of the
interrupt lines from the various MPCs in the system.

Signed-off-by: Peter Maydell <address@hidden>
Message-id: address@hidden


  Commit: af60b29183208123d9aab25acf47e44d54d12a9d
      
https://github.com/qemu/qemu/commit/af60b29183208123d9aab25acf47e44d54d12a9d
  Author: Peter Maydell <address@hidden>
  Date:   2018-06-22 (Fri, 22 Jun 2018)

  Changed paths:
    M hw/arm/iotkit.c
    M include/hw/arm/iotkit.h

  Log Message:
  -----------
  hw/arm/iotkit: Instantiate MPC

Wire up the one MPC that is part of the IoTKit itself. For the
moment we don't wire up its interrupt line.

Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Alex Bennée <address@hidden>
Message-id: address@hidden


  Commit: bb75e16d5e67a764e008d0b73b4ec9f905e5b408
      
https://github.com/qemu/qemu/commit/bb75e16d5e67a764e008d0b73b4ec9f905e5b408
  Author: Peter Maydell <address@hidden>
  Date:   2018-06-22 (Fri, 22 Jun 2018)

  Changed paths:
    M hw/arm/iotkit.c
    M include/hw/arm/iotkit.h

  Log Message:
  -----------
  hw/arm/iotkit: Wire up MPC interrupt lines

The interrupt outputs from the MPC in the IoTKit and the expansion
MPCs in the board must be wired up to the security controller, and
also all ORed together to produce a single line to the NVIC.

Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Alex Bennée <address@hidden>
Message-id: address@hidden


  Commit: 665670aa3ae85444e70888654e7af1eda19598b9
      
https://github.com/qemu/qemu/commit/665670aa3ae85444e70888654e7af1eda19598b9
  Author: Peter Maydell <address@hidden>
  Date:   2018-06-22 (Fri, 22 Jun 2018)

  Changed paths:
    M hw/arm/mps2-tz.c

  Log Message:
  -----------
  hw/arm/mps2-tz.c: Instantiate MPCs

Instantiate and wire up the Memory Protection Controllers
in the MPS2 board itself.

Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Alex Bennée <address@hidden>
Message-id: address@hidden


  Commit: cc2ae7c9de14efd72c6205825eb7cd980ac09c11
      
https://github.com/qemu/qemu/commit/cc2ae7c9de14efd72c6205825eb7cd980ac09c11
  Author: Julia Suvorova <address@hidden>
  Date:   2018-06-22 (Fri, 22 Jun 2018)

  Changed paths:
    M target/arm/cpu.c
    M target/arm/cpu.h

  Log Message:
  -----------
  target/arm: Introduce ARM_FEATURE_M_MAIN

This feature is intended to distinguish ARMv8-M variants: Baseline and
Mainline. ARMv7-M compatibility requires the Main Extension. ARMv6-M
compatibility is provided by all ARMv8-M implementations.

Signed-off-by: Julia Suvorova <address@hidden>
Message-id: address@hidden
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 2aeba0d007d33efa12a6339bb140aa634e0d52eb
      
https://github.com/qemu/qemu/commit/2aeba0d007d33efa12a6339bb140aa634e0d52eb
  Author: Julia Suvorova <address@hidden>
  Date:   2018-06-22 (Fri, 22 Jun 2018)

  Changed paths:
    M target/arm/translate.c

  Log Message:
  -----------
  target/arm: Strict alignment for ARMv6-M and ARMv8-M Baseline

Unlike ARMv7-M, ARMv6-M and ARMv8-M Baseline only supports naturally
aligned memory accesses for load/store instructions.

Signed-off-by: Julia Suvorova <address@hidden>
Message-id: address@hidden
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>


  Commit: b8d880ba6dcca098dc3a5d345a13bebdcce89c90
      
https://github.com/qemu/qemu/commit/b8d880ba6dcca098dc3a5d345a13bebdcce89c90
  Author: Peter Maydell <address@hidden>
  Date:   2018-06-22 (Fri, 22 Jun 2018)

  Changed paths:
    M vl.c

  Log Message:
  -----------
  vl.c: Don't zero-initialize statics for serial_hds

checkpatch reminds us that statics shouldn't be zero-initialized:

ERROR: do not initialise statics to 0 or NULL
#35: FILE: vl.c:157:
+static int num_serial_hds = 0;

ERROR: do not initialise statics to 0 or NULL
#36: FILE: vl.c:158:
+static Chardev **serial_hds = NULL;

I forgot to fix this in 6af2692e86f9fdfb3d; do so now.

Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Thomas Huth <address@hidden>
Message-id: address@hidden


  Commit: 6dad8260e82b69bd278685ee25209f5824360455
      
https://github.com/qemu/qemu/commit/6dad8260e82b69bd278685ee25209f5824360455
  Author: Peter Maydell <address@hidden>
  Date:   2018-06-22 (Fri, 22 Jun 2018)

  Changed paths:
    M hw/xen/xen_pt.h
    M hw/xen/xen_pt_graphics.c
    M hw/xen/xen_pt_load_rom.c

  Log Message:
  -----------
  xen: Don't use memory_region_init_ram_nomigrate() in 
pci_assign_dev_load_option_rom()

The xen pci_assign_dev_load_option_rom() currently creates a RAM
memory region with memory_region_init_ram_nomigrate(), and then
manually registers it with vmstate_register_ram(). In fact for
its only callsite, the 'owner' pointer we use for the init call
and the '&dev->qdev' pointer we use for the vmstate_register_ram()
call refer to the same object. Simplify the function to only
take a pointer to the device once instead of twice, and use
memory_region_init_ram() which automatically does the vmstate
register for us.

Acked-by: Anthony PERARD <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 5fce31220003bbe1b4c7faa0dbf92d131b0a413b
      
https://github.com/qemu/qemu/commit/5fce31220003bbe1b4c7faa0dbf92d131b0a413b
  Author: Peter Maydell <address@hidden>
  Date:   2018-06-22 (Fri, 22 Jun 2018)

  Changed paths:
    M MAINTAINERS
    M default-configs/arm-softmmu.mak
    M hw/arm/iotkit.c
    M hw/arm/mps2-tz.c
    M hw/arm/virt-acpi-build.c
    M hw/arm/virt.c
    M hw/arm/xlnx-zcu102.c
    M hw/arm/xlnx-zynqmp.c
    M hw/intc/arm_gic_kvm.c
    M hw/intc/arm_gicv3.c
    M hw/intc/arm_gicv3_common.c
    M hw/intc/arm_gicv3_dist.c
    M hw/intc/arm_gicv3_its_kvm.c
    M hw/intc/arm_gicv3_kvm.c
    M hw/intc/arm_gicv3_redist.c
    M hw/misc/Makefile.objs
    M hw/misc/iotkit-secctl.c
    M hw/misc/trace-events
    A hw/misc/tz-mpc.c
    M hw/xen/xen_pt.h
    M hw/xen/xen_pt_graphics.c
    M hw/xen/xen_pt_load_rom.c
    M include/hw/arm/iotkit.h
    M include/hw/arm/virt.h
    M include/hw/intc/arm_gicv3_common.h
    M include/hw/misc/iotkit-secctl.h
    A include/hw/misc/tz-mpc.h
    M include/standard-headers/linux/pci_regs.h
    M include/standard-headers/linux/virtio_gpu.h
    M include/standard-headers/linux/virtio_net.h
    M linux-headers/LICENSES/exceptions/Linux-syscall-note
    M linux-headers/LICENSES/preferred/GPL-2.0
    M linux-headers/asm-arm/kvm.h
    M linux-headers/asm-arm/unistd-common.h
    M linux-headers/asm-arm64/kvm.h
    M linux-headers/asm-generic/unistd.h
    M linux-headers/asm-powerpc/unistd.h
    M linux-headers/asm-x86/unistd_32.h
    M linux-headers/asm-x86/unistd_64.h
    M linux-headers/asm-x86/unistd_x32.h
    M linux-headers/linux/kvm.h
    M linux-headers/linux/psp-sev.h
    M target/arm/cpu.c
    M target/arm/cpu.h
    M target/arm/kvm.c
    M target/arm/kvm_arm.h
    M target/arm/translate.c
    M vl.c

  Log Message:
  -----------
  Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20180622' 
into staging

target-arm queue:
 * hw/intc/arm_gicv3: fix wrong values when reading IPRIORITYR
 * target/arm: fix read of freed memory in kvm_arm_machine_init_done()
 * virt: support up to 512 CPUs
 * virt: support 256MB ECAM PCI region (for more PCI devices)
 * xlnx-zynqmp: Use Cortex-R5F, not Cortex-R5
 * mps2-tz: Implement and use the TrustZone Memory Protection Controller
 * target/arm: enforce alignment checking for v6M cores
 * xen: Don't use memory_region_init_ram_nomigrate() in 
pci_assign_dev_load_option_rom()
 * vl.c: Don't zero-initialize statics for serial_hds

# gpg: Signature made Fri 22 Jun 2018 13:56:00 BST
# gpg:                using RSA key 3C2525ED14360CDE
# gpg: Good signature from "Peter Maydell <address@hidden>"
# gpg:                 aka "Peter Maydell <address@hidden>"
# gpg:                 aka "Peter Maydell <address@hidden>"
# Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83  15CF 3C25 25ED 1436 0CDE

* remotes/pmaydell/tags/pull-target-arm-20180622: (28 commits)
  xen: Don't use memory_region_init_ram_nomigrate() in 
pci_assign_dev_load_option_rom()
  vl.c: Don't zero-initialize statics for serial_hds
  target/arm: Strict alignment for ARMv6-M and ARMv8-M Baseline
  target/arm: Introduce ARM_FEATURE_M_MAIN
  hw/arm/mps2-tz.c: Instantiate MPCs
  hw/arm/iotkit: Wire up MPC interrupt lines
  hw/arm/iotkit: Instantiate MPC
  hw/misc/iotkit-secctl.c: Implement SECMPCINTSTATUS
  hw/misc/tz_mpc.c: Honour the BLK_LUT settings in translate
  hw/misc/tz-mpc.c: Implement correct blocked-access behaviour
  hw/misc/tz-mpc.c: Implement registers
  hw/misc/tz-mpc.c: Implement the Arm TrustZone Memory Protection Controller
  xlnx-zynqmp: Swap Cortex-R5 for Cortex-R5F
  target-arm: Add the Cortex-R5F
  hw/arm/virt: Increase max_cpus to 512
  hw/arm/virt: Use 256MB ECAM region by default
  hw/arm/virt: Add virt-3.0 machine type
  hw/arm/virt: Add a new 256MB ECAM region
  hw/arm/virt: Register two redistributor regions when necessary
  hw/arm/virt-acpi-build: Advertise one or two GICR structures
  ...

Signed-off-by: Peter Maydell <address@hidden>


Compare: https://github.com/qemu/qemu/compare/c52e53f429aa...5fce31220003
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