[Qemu-commits] [qemu/qemu] e40df9: target/mips: Fix MIPS64 MFC0 UserLocal on BE host

[GitHub]

  Branch: refs/heads/master
  Home:   https://github.com/qemu/qemu
  Commit: e40df9a80bb7cdb0a4ca650985fa9fe572097fa7
      
https://github.com/qemu/qemu/commit/e40df9a80bb7cdb0a4ca650985fa9fe572097fa7
  Author: James Hogan <address@hidden>
  Date:   2017-07-20 (Thu, 20 Jul 2017)

  Changed paths:
    M target/mips/translate.c

  Log Message:
  -----------
  target/mips: Fix MIPS64 MFC0 UserLocal on BE host

Using MFC0 to read CP0_UserLocal uses tcg_gen_ld32s_tl, however
CP0_UserLocal is a target_ulong. On a big endian host with a MIPS64
target this reads and sign extends the more significant half of the
64-bit register.

Fix this by using ld_tl to load the whole target_ulong and ext32s_tl to
sign extend it, as done for various other target_ulong COP0 registers.

Fixes: d279279e2b5c ("target-mips: implement UserLocal Register")
Signed-off-by: James Hogan <address@hidden>
Cc: Yongbok Kim <address@hidden>
Cc: Aurelien Jarno <address@hidden>
Cc: Petar Jovanovic <address@hidden>
Reviewed-by: Yongbok Kim <address@hidden>
Signed-off-by: Yongbok Kim <address@hidden>


  Commit: eff6ff9431aa9776062a5f4a08d1f6503ca9995a
      
https://github.com/qemu/qemu/commit/eff6ff9431aa9776062a5f4a08d1f6503ca9995a
  Author: James Hogan <address@hidden>
  Date:   2017-07-20 (Thu, 20 Jul 2017)

  Changed paths:
    M target/mips/op_helper.c

  Log Message:
  -----------
  target/mips: Fix TLBWI shadow flush for EHINV,XI,RI

Writing specific TLB entries with TLBWI flushes shadow TLB entries
unless an existing entry is having its access permissions upgraded. This
is necessary as software would from then on expect the previous mapping
in that entry to no longer be in effect (even if QEMU has quietly
evicted it to the shadow TLB on a TLBWR).

However it won't do this if only EHINV, XI, or RI bits have been set,
even if that results in a reduction of permissions, so add the necessary
checks to invoke the flush when these bits are set.

Fixes: 2fb58b73746e ("target-mips: add RI and XI fields to TLB entry")
Fixes: 9456c2fbcd82 ("target-mips: add TLBINV support")
Signed-off-by: James Hogan <address@hidden>
Cc: Yongbok Kim <address@hidden>
Cc: Aurelien Jarno <address@hidden>
Tested-by: Yongbok Kim <address@hidden>
address@hidden:
  cosmetic changes]
Signed-off-by: Yongbok Kim <address@hidden>


  Commit: 9658e4c342e6ae0d775101f8f6bb6efb16789af1
      
https://github.com/qemu/qemu/commit/9658e4c342e6ae0d775101f8f6bb6efb16789af1
  Author: James Hogan <address@hidden>
  Date:   2017-07-20 (Thu, 20 Jul 2017)

  Changed paths:
    M target/mips/helper.c
    M target/mips/op_helper.c

  Log Message:
  -----------
  target/mips: Weaken TLB flush on UX,SX,KX,ASID changes

There is no need to invalidate any shadow TLB entries when the ASID
changes or when access to one of the 64-bit segments has been disabled,
since doing so doesn't reveal to software whether any TLB entries have
been evicted into the shadow half of the TLB.

Therefore weaken the tlb flushes in these cases to only flush the QEMU
TLB.

Signed-off-by: James Hogan <address@hidden>
Cc: Yongbok Kim <address@hidden>
Cc: Aurelien Jarno <address@hidden>
Tested-by: Yongbok Kim <address@hidden>
Signed-off-by: Yongbok Kim <address@hidden>


  Commit: 74dbf824a1313b6064bbebb981a7440951d70896
      
https://github.com/qemu/qemu/commit/74dbf824a1313b6064bbebb981a7440951d70896
  Author: James Hogan <address@hidden>
  Date:   2017-07-20 (Thu, 20 Jul 2017)

  Changed paths:
    M target/mips/cpu.h
    M target/mips/helper.c
    M target/mips/machine.c
    M target/mips/op_helper.c
    M target/mips/translate.c
    M target/mips/translate_init.c

  Log Message:
  -----------
  target/mips: Add CP0_Ebase.WG (write gate) support

Add support for the CP0_EBase.WG bit, which allows upper bits to be
written (bits 31:30 on MIPS32, or bits 63:30 on MIPS64), along with the
CP0_Config5.CV bit to control whether the exception vector for Cache
Error exceptions is forced into KSeg1.

This is necessary on MIPS32 to support Segmentation Control and Enhanced
Virtual Addressing (EVA) extensions (where KSeg1 addresses may not
represent an unmapped uncached segment).

It is also useful on MIPS64 to allow the exception base to reside in
XKPhys, and possibly out of range of KSEG0 and KSEG1.

Signed-off-by: James Hogan <address@hidden>
Cc: Yongbok Kim <address@hidden>
Cc: Aurelien Jarno <address@hidden>
Reviewed-by: Yongbok Kim <address@hidden>
address@hidden:
  minor changes]
Signed-off-by: Yongbok Kim <address@hidden>


  Commit: dd4096cd2ccc19384770f336c930259da7a54980
      
https://github.com/qemu/qemu/commit/dd4096cd2ccc19384770f336c930259da7a54980
  Author: James Hogan <address@hidden>
  Date:   2017-07-20 (Thu, 20 Jul 2017)

  Changed paths:
    M target/mips/translate.c

  Log Message:
  -----------
  target/mips: Prepare loads/stores for EVA

EVA load and store instructions access the user mode address map, so
they need to use mem_idx of MIPS_HFLAG_UM. Update the various utility
functions to allow mem_idx to be more easily overridden from the
decoding logic.

Specifically we add a mem_idx argument to the op_ld/st_* helpers used
for atomics, and a mem_idx local variable to gen_ld(), gen_st(), and
gen_st_cond().

Signed-off-by: James Hogan <address@hidden>
Reviewed-by: Yongbok Kim <address@hidden>
Cc: Yongbok Kim <address@hidden>
Cc: Aurelien Jarno <address@hidden>
Signed-off-by: Yongbok Kim <address@hidden>


  Commit: 7696414729b2d0f870c80ad1dd637d854bc78847
      
https://github.com/qemu/qemu/commit/7696414729b2d0f870c80ad1dd637d854bc78847
  Author: James Hogan <address@hidden>
  Date:   2017-07-20 (Thu, 20 Jul 2017)

  Changed paths:
    M target/mips/translate.c

  Log Message:
  -----------
  target/mips: Decode MIPS32 EVA load & store instructions

Implement decoding of MIPS32 EVA loads and stores. These access the user
address space from kernel mode when implemented, so for each instruction
we need to check that EVA is available from Config5.EVA & check for
sufficient COP0 privilege (with the new check_eva()), and then override
the mem_idx used for the operation.

Unfortunately some Loongson 2E instructions use overlapping encodings,
so we must be careful not to prevent those from being decoded when EVA
is absent.

Signed-off-by: James Hogan <address@hidden>
Cc: Yongbok Kim <address@hidden>
Cc: Aurelien Jarno <address@hidden>
Reviewed-by: Yongbok Kim <address@hidden>
Signed-off-by: Yongbok Kim <address@hidden>


  Commit: 8fffc64696783b1ff1d17262d098976479895660
      
https://github.com/qemu/qemu/commit/8fffc64696783b1ff1d17262d098976479895660
  Author: James Hogan <address@hidden>
  Date:   2017-07-20 (Thu, 20 Jul 2017)

  Changed paths:
    M target/mips/translate.c

  Log Message:
  -----------
  target/mips: Decode microMIPS EVA load & store instructions

Implement decoding of microMIPS EVA load and store instruction groups in
the POOL31C pool. These use the same gen_ld(), gen_st(), gen_st_cond()
helpers as the MIPS32 decoding, passing the equivalent MIPS32 opcodes as
opc.

Signed-off-by: James Hogan <address@hidden>
Cc: Yongbok Kim <address@hidden>
Cc: Aurelien Jarno <address@hidden>
Reviewed-by: Yongbok Kim <address@hidden>
Signed-off-by: Yongbok Kim <address@hidden>


  Commit: 9fbf4a58c90183b30bb2c8ad971ccce7e6716a16
      
https://github.com/qemu/qemu/commit/9fbf4a58c90183b30bb2c8ad971ccce7e6716a16
  Author: James Hogan <address@hidden>
  Date:   2017-07-20 (Thu, 20 Jul 2017)

  Changed paths:
    M target/mips/helper.c

  Log Message:
  -----------
  target/mips: Check memory permissions with mem_idx

When performing virtual to physical address translation, check the
required privilege level based on the mem_idx rather than the mode in
the hflags. This will allow EVA loads & stores to operate safely only on
user memory from kernel mode.

For the cases where the mmu_idx doesn't need to be overridden
(mips_cpu_get_phys_page_debug() and cpu_mips_translate_address()), we
calculate the required mmu_idx using cpu_mmu_index(). Note that this
only tests the MIPS_HFLAG_KSU bits rather than MIPS_HFLAG_MODE, so we
don't test the debug mode hflag MIPS_HFLAG_DM any longer. This should be
fine as get_physical_address() only compares against MIPS_HFLAG_UM and
MIPS_HFLAG_SM, neither of which should get set by compute_hflags() when
MIPS_HFLAG_DM is set.

Signed-off-by: James Hogan <address@hidden>
Reviewed-by: Yongbok Kim <address@hidden>
Cc: Aurelien Jarno <address@hidden>
Signed-off-by: Yongbok Kim <address@hidden>


  Commit: b0fc6003224543d2bdb172eca752656a6223e4a1
      
https://github.com/qemu/qemu/commit/b0fc6003224543d2bdb172eca752656a6223e4a1
  Author: James Hogan <address@hidden>
  Date:   2017-07-20 (Thu, 20 Jul 2017)

  Changed paths:
    M target/mips/cpu.h
    M target/mips/op_helper.c
    M target/mips/translate.c

  Log Message:
  -----------
  target/mips: Abstract mmu_idx from hflags

The MIPS mmu_idx is sometimes calculated from hflags without an env
pointer available as cpu_mmu_index() requires.

Create a common hflags_mmu_index() for the purpose of this calculation
which can operate on any hflags, not just with an env pointer, and
update cpu_mmu_index() itself and gen_intermediate_code() to use it.

Also update debug_post_eret() and helper_mtc0_status() to log the MMU
mode with the status change (SM, UM, or nothing for kernel mode) based
on cpu_mmu_index() rather than directly testing hflags.

This will also allow the logic to be more easily updated when a new MMU
mode is added.

Signed-off-by: James Hogan <address@hidden>
Reviewed-by: Yongbok Kim <address@hidden>
Cc: Aurelien Jarno <address@hidden>
Signed-off-by: Yongbok Kim <address@hidden>


  Commit: 42c86612d507c2a8789f2b8d920a244693c4ef7b
      
https://github.com/qemu/qemu/commit/42c86612d507c2a8789f2b8d920a244693c4ef7b
  Author: James Hogan <address@hidden>
  Date:   2017-07-20 (Thu, 20 Jul 2017)

  Changed paths:
    M target/mips/cpu.h
    M target/mips/op_helper.c

  Log Message:
  -----------
  target/mips: Add an MMU mode for ERL

The segmentation control feature allows a legacy memory segment to
become unmapped uncached at error level (according to CP0_Status.ERL),
and in fact the user segment is already treated in this way by QEMU.

Add a new MMU mode for this state so that QEMU's mappings don't persist
between ERL=0 and ERL=1.

Signed-off-by: James Hogan <address@hidden>
Reviewed-by: Yongbok Kim <address@hidden>
Cc: Aurelien Jarno <address@hidden>
address@hidden:
  cosmetic changes]
Signed-off-by: Yongbok Kim <address@hidden>


  Commit: cec56a733dd2c3fa81dbedbecf03922258747f7d
      
https://github.com/qemu/qemu/commit/cec56a733dd2c3fa81dbedbecf03922258747f7d
  Author: James Hogan <address@hidden>
  Date:   2017-07-20 (Thu, 20 Jul 2017)

  Changed paths:
    M target/mips/cpu.h
    M target/mips/helper.h
    M target/mips/machine.c
    M target/mips/op_helper.c
    M target/mips/translate.c

  Log Message:
  -----------
  target/mips: Add segmentation control registers

The optional segmentation control registers CP0_SegCtl0, CP0_SegCtl1 &
CP0_SegCtl2 control the behaviour and required privilege of the legacy
virtual memory segments.

Add them to the CP0 interface so they can be read and written when
CP0_Config3.SC=1, and initialise them to describe the standard legacy
layout so they can be used in future patches regardless of whether they
are exposed to the guest.

Signed-off-by: James Hogan <address@hidden>
Cc: Yongbok Kim <address@hidden>
Cc: Aurelien Jarno <address@hidden>
Reviewed-by: Yongbok Kim <address@hidden>
Signed-off-by: Yongbok Kim <address@hidden>


  Commit: 480e79aedd322fcfac17052caff21626ea7c78e2
      
https://github.com/qemu/qemu/commit/480e79aedd322fcfac17052caff21626ea7c78e2
  Author: James Hogan <address@hidden>
  Date:   2017-07-20 (Thu, 20 Jul 2017)

  Changed paths:
    M target/mips/helper.c

  Log Message:
  -----------
  target/mips: Implement segmentation control

Implement the optional segmentation control feature in the virtual to
physical address translation code.

The fixed legacy segment and xkphys handling is replaced with a dynamic
layout based on the segmentation control registers (which should be set
up even when the feature is not exposed to the guest).

Signed-off-by: James Hogan <address@hidden>
Cc: Yongbok Kim <address@hidden>
Cc: Aurelien Jarno <address@hidden>
Reviewed-by: Yongbok Kim <address@hidden>
address@hidden:
  cosmetic changes]
Signed-off-by: Yongbok Kim <address@hidden>


  Commit: 574da58e4678b3c09048f268821295422d8cde6d
      
https://github.com/qemu/qemu/commit/574da58e4678b3c09048f268821295422d8cde6d
  Author: James Hogan <address@hidden>
  Date:   2017-07-21 (Fri, 21 Jul 2017)

  Changed paths:
    M target/mips/translate_init.c

  Log Message:
  -----------
  target/mips: Add EVA support to P5600

Add the Enhanced Virtual Addressing (EVA) feature to the P5600 core
configuration, along with the related Segmentation Control (SC) feature
and writable CP0_EBase.WG bit.

This allows it to run Malta EVA kernels.

Signed-off-by: James Hogan <address@hidden>
Reviewed-by: Yongbok Kim <address@hidden>
Cc: Aurelien Jarno <address@hidden>
Signed-off-by: Yongbok Kim <address@hidden>


  Commit: bad63a8008a0aaefcd00542c89bee01623d7c9de
      
https://github.com/qemu/qemu/commit/bad63a8008a0aaefcd00542c89bee01623d7c9de
  Author: James Hogan <address@hidden>
  Date:   2017-07-21 (Fri, 21 Jul 2017)

  Changed paths:
    M target/mips/translate_init.c

  Log Message:
  -----------
  target/mips: Enable CP0_EBase.WG on MIPS64 CPUs

Enable the CP0_EBase.WG (write gate) on the I6400 and MIPS64R2-generic
CPUs. This allows 64-bit guests to run KVM itself, which uses
CP0_EBase.WG to point CP0_EBase at XKPhys.

Signed-off-by: James Hogan <address@hidden>
Cc: Yongbok Kim <address@hidden>
Cc: Aurelien Jarno <address@hidden>
Reviewed-by: Yongbok Kim <address@hidden>
Signed-off-by: Yongbok Kim <address@hidden>


  Commit: ff9b5475021d230eef39ec15af56c603eec1b82f
      
https://github.com/qemu/qemu/commit/ff9b5475021d230eef39ec15af56c603eec1b82f
  Author: Peter Maydell <address@hidden>
  Date:   2017-07-21 (Fri, 21 Jul 2017)

  Changed paths:
    M target/mips/cpu.h
    M target/mips/helper.c
    M target/mips/helper.h
    M target/mips/machine.c
    M target/mips/op_helper.c
    M target/mips/translate.c
    M target/mips/translate_init.c

  Log Message:
  -----------
  Merge remote-tracking branch 'remotes/yongbok/tags/mips-20170721' into staging

MIPS patches 2017-07-21

Changes:
* Add Enhanced Virtual Addressing (EVA) support

# gpg: Signature made Fri 21 Jul 2017 03:25:15 BST
# gpg:                using RSA key 0x2238EB86D5F797C2
# gpg: Good signature from "Yongbok Kim <address@hidden>"
# gpg: WARNING: This key is not certified with a trusted signature!
# gpg:          There is no indication that the signature belongs to the owner.
# Primary key fingerprint: 8600 4CF5 3415 A5D9 4CFA  2B5C 2238 EB86 D5F7 97C2

* remotes/yongbok/tags/mips-20170721:
  target/mips: Enable CP0_EBase.WG on MIPS64 CPUs
  target/mips: Add EVA support to P5600
  target/mips: Implement segmentation control
  target/mips: Add segmentation control registers
  target/mips: Add an MMU mode for ERL
  target/mips: Abstract mmu_idx from hflags
  target/mips: Check memory permissions with mem_idx
  target/mips: Decode microMIPS EVA load & store instructions
  target/mips: Decode MIPS32 EVA load & store instructions
  target/mips: Prepare loads/stores for EVA
  target/mips: Add CP0_Ebase.WG (write gate) support
  target/mips: Weaken TLB flush on UX,SX,KX,ASID changes
  target/mips: Fix TLBWI shadow flush for EHINV,XI,RI
  target/mips: Fix MIPS64 MFC0 UserLocal on BE host

Signed-off-by: Peter Maydell <address@hidden>


Compare: https://github.com/qemu/qemu/compare/14e167530adf...ff9b5475021d