[Qemu-commits] [qemu/qemu] 499ca1: hw/misc: Add Exynos4210 Pseudo Random Number Gener...

[GitHub]

  Branch: refs/heads/master
  Home:   https://github.com/qemu/qemu
  Commit: 499ca137929418bcc42ce83e2ae06be8242b9cb9
      
https://github.com/qemu/qemu/commit/499ca137929418bcc42ce83e2ae06be8242b9cb9
  Author: Krzysztof Kozlowski <address@hidden>
  Date:   2017-07-11 (Tue, 11 Jul 2017)

  Changed paths:
    M hw/arm/exynos4210.c
    M hw/misc/Makefile.objs
    A hw/misc/exynos4210_rng.c

  Log Message:
  -----------
  hw/misc: Add Exynos4210 Pseudo Random Number Generator

Add emulation for Exynos4210 Pseudo Random Number Generator which could
work on fixed seeds or with seeds provided by True Random Number
Generator block inside the SoC.

Implement only the fixed seeds part of it in polling mode (no
interrupts).

Emulation tested with two independent Linux kernel exynos-rng drivers:
1. New kcapi-rng interface (targeting Linux v4.12),
2. Old hwrng inteface
   # echo "exynos" > /sys/class/misc/hw_random/rng_current
   # dd if=/dev/hwrng of=/dev/null bs=1 count=16

Signed-off-by: Krzysztof Kozlowski <address@hidden>
Message-id: address@hidden
Reviewed-by: Peter Maydell <address@hidden>
[PMM: wrapped a few overlong lines; more efficient implementation
 of exynos4210_rng_seed_ready()]
Signed-off-by: Peter Maydell <address@hidden>


  Commit: f986ee1d43004a336197ee012e901f44bba04785
      
https://github.com/qemu/qemu/commit/f986ee1d43004a336197ee012e901f44bba04785
  Author: Joel Stanley <address@hidden>
  Date:   2017-07-11 (Tue, 11 Jul 2017)

  Changed paths:
    M hw/arm/aspeed_soc.c
    M include/hw/arm/aspeed_soc.h

  Log Message:
  -----------
  aspeed: Register all watchdogs

The ast2400 contains two and the ast2500 contains three watchdogs.
Add this information to the AspeedSoCInfo and realise the correct number
of watchdogs for that each SoC type.

Signed-off-by: Joel Stanley <address@hidden>
Reviewed-by: Cédric Le Goater <address@hidden>
Tested-by: Cédric Le Goater <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 5d721b785fbe80170fc756e9444cf751d3a47568
      
https://github.com/qemu/qemu/commit/5d721b785fbe80170fc756e9444cf751d3a47568
  Author: Alexander Graf <address@hidden>
  Date:   2017-07-11 (Tue, 11 Jul 2017)

  Changed paths:
    M accel/kvm/kvm-all.c
    M accel/stubs/kvm-stub.c
    M hw/intc/arm_gic.c
    M include/sysemu/kvm.h
    M target/arm/cpu.h
    M target/arm/kvm.c

  Log Message:
  -----------
  ARM: KVM: Enable in-kernel timers with user space gic

When running with KVM enabled, you can choose between emulating the
gic in kernel or user space. If the kernel supports in-kernel virtualization
of the interrupt controller, it will default to that. If not, if will
default to user space emulation.

Unfortunately when running in user mode gic emulation, we miss out on
interrupt events which are only available from kernel space, such as the timer.
This patch leverages the new kernel/user space pending line synchronization for
timer events. It does not handle PMU events yet.

Signed-off-by: Alexander Graf <address@hidden>
Reviewed-by: Andrew Jones <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 792dac309c8660306557ba058b8b5a6a75ab3c1f
      
https://github.com/qemu/qemu/commit/792dac309c8660306557ba058b8b5a6a75ab3c1f
  Author: Peter Maydell <address@hidden>
  Date:   2017-07-11 (Tue, 11 Jul 2017)

  Changed paths:
    M target/arm/helper.c

  Log Message:
  -----------
  target-arm: v7M: ignore writes to CONTROL.SPSEL from Thread mode

For v7M, writes to the CONTROL register are only permitted for
privileged code. However even if the code is privileged, the
write must not affect the SPSEL bit in the CONTROL register
if the CPU is in Thread mode (as documented in the pseudocode
for the MSR instruction). Implement this, instead of permitting
SPSEL to be written in all cases.

This was causing mbed applications not to run, because the
RTX RTOS they use relies on this behaviour.

Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
Message-id: address@hidden


  Commit: 6e2c46334385c7e295ac883c801c81b4925fb54f
      
https://github.com/qemu/qemu/commit/6e2c46334385c7e295ac883c801c81b4925fb54f
  Author: Peter Maydell <address@hidden>
  Date:   2017-07-13 (Thu, 13 Jul 2017)

  Changed paths:
    M accel/kvm/kvm-all.c
    M accel/stubs/kvm-stub.c
    M hw/arm/aspeed_soc.c
    M hw/arm/exynos4210.c
    M hw/intc/arm_gic.c
    M hw/misc/Makefile.objs
    A hw/misc/exynos4210_rng.c
    M include/hw/arm/aspeed_soc.h
    M include/sysemu/kvm.h
    M target/arm/cpu.h
    M target/arm/helper.c
    M target/arm/kvm.c

  Log Message:
  -----------
  Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20170711' 
into staging

target-arm queue:
 * v7M: ignore writes to CONTROL.SPSEL from Thread mode
 * KVM: Enable in-kernel timers with user space gic
 * aspeed: Register all watchdogs
 * hw/misc: Add Exynos4210 Pseudo Random Number Generator

# gpg: Signature made Tue 11 Jul 2017 11:28:15 BST
# gpg:                using RSA key 0x3C2525ED14360CDE
# gpg: Good signature from "Peter Maydell <address@hidden>"
# gpg:                 aka "Peter Maydell <address@hidden>"
# gpg:                 aka "Peter Maydell <address@hidden>"
# Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83  15CF 3C25 25ED 1436 0CDE

* remotes/pmaydell/tags/pull-target-arm-20170711:
  target-arm: v7M: ignore writes to CONTROL.SPSEL from Thread mode
  ARM: KVM: Enable in-kernel timers with user space gic
  aspeed: Register all watchdogs
  hw/misc: Add Exynos4210 Pseudo Random Number Generator

Signed-off-by: Peter Maydell <address@hidden>


Compare: https://github.com/qemu/qemu/compare/31fe1c414501...6e2c46334385