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[Qemu-commits] [qemu/qemu] 723733: target-tricore: fix save_context_uppe
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GitHub |
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[Qemu-commits] [qemu/qemu] 723733: target-tricore: fix save_context_upper using env->... |
Date: |
Thu, 25 Feb 2016 06:30:03 -0800 |
Branch: refs/heads/master
Home: https://github.com/qemu/qemu
Commit: 723733575b90089c51adefde41875310052031c2
https://github.com/qemu/qemu/commit/723733575b90089c51adefde41875310052031c2
Author: Bastian Koppelmann <address@hidden>
Date: 2016-02-25 (Thu, 25 Feb 2016)
Changed paths:
M target-tricore/op_helper.c
Log Message:
-----------
target-tricore: fix save_context_upper using env->PSW
If the cached bits for C, V, SV, AV, or SAV were set, they would
not be saved during the context save since env->PSW was stored instead
of properly reading them using psw_read().
Reviewed-by: Richard Henderson <address@hidden>
Signed-off-by: Bastian Koppelmann <address@hidden>
Commit: 5dc1fbae707513f9664aa88940a2cd52b064cda2
https://github.com/qemu/qemu/commit/5dc1fbae707513f9664aa88940a2cd52b064cda2
Author: Bastian Koppelmann <address@hidden>
Date: 2016-02-25 (Thu, 25 Feb 2016)
Changed paths:
M target-tricore/helper.c
Log Message:
-----------
target-tricore: Fix wrong precedences on psw_write
Wrong braces on the restore of the cached TCGv SV and V bit could lead to
a wrong PSW. While at this it removes unnecessary braces for the restore
of the cached TCGv AV and SAV bits.
Signed-off-by: Bastian Koppelmann <address@hidden>
Commit: 518d7fd2a098730669c0a0707c031dcfe52ece9a
https://github.com/qemu/qemu/commit/518d7fd2a098730669c0a0707c031dcfe52ece9a
Author: Bastian Koppelmann <address@hidden>
Date: 2016-02-25 (Thu, 25 Feb 2016)
Changed paths:
M target-tricore/cpu.h
M target-tricore/helper.h
M target-tricore/op_helper.c
M target-tricore/translate.c
Log Message:
-----------
target-tricore: Add trap handling & SOVF/OVF traps
Add the infrastructure needed to generate and handle traps and
implement the generation of SOVF and OVF traps.
Reviewed-by: Richard Henderson <address@hidden>
Signed-off-by: Bastian Koppelmann <address@hidden>
Message-Id: <address@hidden>
Commit: 3292b4477fe7a52e69615377bb35945cbae02894
https://github.com/qemu/qemu/commit/3292b4477fe7a52e69615377bb35945cbae02894
Author: Bastian Koppelmann <address@hidden>
Date: 2016-02-25 (Thu, 25 Feb 2016)
Changed paths:
M target-tricore/op_helper.c
Log Message:
-----------
target-tricore: add context managment trap generation
Reviewed-by: Richard Henderson <address@hidden>
Signed-off-by: Bastian Koppelmann <address@hidden>
Message-Id: <address@hidden>
Commit: f678f671ba654d4610f0e43d175c8c1b2fad10df
https://github.com/qemu/qemu/commit/f678f671ba654d4610f0e43d175c8c1b2fad10df
Author: Bastian Koppelmann <address@hidden>
Date: 2016-02-25 (Thu, 25 Feb 2016)
Changed paths:
M target-tricore/translate.c
Log Message:
-----------
target-tricore: add illegal opcode trap generation
Reviewed-by: Richard Henderson <address@hidden>
Signed-off-by: Bastian Koppelmann <address@hidden>
Message-Id: <address@hidden>
Commit: 828066c78a02a98bc395d125002b2d7a888285bb
https://github.com/qemu/qemu/commit/828066c78a02a98bc395d125002b2d7a888285bb
Author: Bastian Koppelmann <address@hidden>
Date: 2016-02-25 (Thu, 25 Feb 2016)
Changed paths:
M target-tricore/translate.c
Log Message:
-----------
target-tricore: add opd trap generation
If an instruction uses a 64 bit register which consists of an even-odd pair
of 32 bit registers and if the register specifier in the instruction is
odd an opd trap is raised.
Reviewed-by: Richard Henderson <address@hidden>
Signed-off-by: Bastian Koppelmann <address@hidden>
Message-Id: <address@hidden>
Commit: 774ae4254d3910f1c94ad6ed44d14cbea0e6a2f2
https://github.com/qemu/qemu/commit/774ae4254d3910f1c94ad6ed44d14cbea0e6a2f2
Author: Peter Maydell <address@hidden>
Date: 2016-02-25 (Thu, 25 Feb 2016)
Changed paths:
M target-tricore/cpu.h
M target-tricore/helper.c
M target-tricore/helper.h
M target-tricore/op_helper.c
M target-tricore/translate.c
Log Message:
-----------
Merge remote-tracking branch 'remotes/bkoppelmann/tags/pull-tricore-20160225'
into staging
TriCore bugfixes and synchronous trap implementation
# gpg: Signature made Thu 25 Feb 2016 11:57:41 GMT using RSA key ID 6B69CA14
# gpg: Good signature from "Bastian Koppelmann <address@hidden>"
* remotes/bkoppelmann/tags/pull-tricore-20160225:
target-tricore: add opd trap generation
target-tricore: add illegal opcode trap generation
target-tricore: add context managment trap generation
target-tricore: Add trap handling & SOVF/OVF traps
target-tricore: Fix wrong precedences on psw_write
target-tricore: fix save_context_upper using env->PSW
Signed-off-by: Peter Maydell <address@hidden>
Compare: https://github.com/qemu/qemu/compare/df215b59d907...774ae4254d39
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