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[Qemu-commits] [qemu/qemu] 71f303: target-mips: Use tcg_gen_extrh_i64_i3

From: GitHub
Subject: [Qemu-commits] [qemu/qemu] 71f303: target-mips: Use tcg_gen_extrh_i64_i32
Date: Fri, 18 Sep 2015 07:00:06 -0700 
  Branch: refs/heads/master
  Home:   https://github.com/qemu/qemu
  Commit: 71f303cd246ae22ce6fdacb3801b5abbca25c409
      
https://github.com/qemu/qemu/commit/71f303cd246ae22ce6fdacb3801b5abbca25c409
  Author: Richard Henderson <address@hidden>
  Date:   2015-09-18 (Fri, 18 Sep 2015)

  Changed paths:
    M target-mips/translate.c

  Log Message:
  -----------
  target-mips: Use tcg_gen_extrh_i64_i32

We can tidy gen_load_fpr32h, as well as introduce a helper
to cleanup the MACC instructions.

Signed-off-by: Richard Henderson <address@hidden>
Reviewed-by: Leon Alrae <address@hidden>
Signed-off-by: Leon Alrae <address@hidden>


  Commit: ca6c7803d2beae43299a80f4549d36579881fc0b
      
https://github.com/qemu/qemu/commit/ca6c7803d2beae43299a80f4549d36579881fc0b
  Author: Petar Jovanovic <address@hidden>
  Date:   2015-09-18 (Fri, 18 Sep 2015)

  Changed paths:
    M target-mips/translate.c

  Log Message:
  -----------
  target-mips: remove wrong checks for recip.fmt and rsqrt.fmt

Instructions recip.{s|d} and rsqrt.{s|d} do not require 64-bit FPU neither
they require any particular mode for its FPU. This patch removes the checks
that may break a program that uses these instructions.

Signed-off-by: Petar Jovanovic <address@hidden>
Reviewed-by: Leon Alrae <address@hidden>
Signed-off-by: Leon Alrae <address@hidden>


  Commit: cdfcad788394ff53e317043e07b8e34f4987c659
      
https://github.com/qemu/qemu/commit/cdfcad788394ff53e317043e07b8e34f4987c659
  Author: Alex Smith <address@hidden>
  Date:   2015-09-18 (Fri, 18 Sep 2015)

  Changed paths:
    M target-mips/op_helper.c

  Log Message:
  -----------
  target-mips: Fix RDHWR on CP0.Count

For RDHWR on the CP0.Count register, env->CP0_Count was being returned.
This value is a delta against the QEMU_CLOCK_VIRTUAL clock, not the
correct current value of CP0.Count. Use cpu_mips_get_count() instead.

Signed-off-by: Alex Smith <address@hidden>
Cc: Aurelien Jarno <address@hidden>
Cc: Leon Alrae <address@hidden>
Reviewed-by: Leon Alrae <address@hidden>
Reviewed-by: Aurelien Jarno <address@hidden>
Signed-off-by: Leon Alrae <address@hidden>


  Commit: 9d68ac14dab3f5af33a6b23458941dc6fb261fce
      
https://github.com/qemu/qemu/commit/9d68ac14dab3f5af33a6b23458941dc6fb261fce
  Author: Aurelien Jarno <address@hidden>
  Date:   2015-09-18 (Fri, 18 Sep 2015)

  Changed paths:
    M target-mips/translate.c

  Log Message:
  -----------
  target-mips: get rid of MIPS_DEBUG

MIPS_DEBUG is a define used to dump the instruction disassembling. It
has to be defined at compile time. In practice I believe it's more
efficient to just look at the instruction disassembly and op dump using
-d in_asm,op. This patch therefore removes the corresponding code, which
clutters translate.c.

Cc: Leon Alrae <address@hidden>
Signed-off-by: Aurelien Jarno <address@hidden>
Reviewed-by: Leon Alrae <address@hidden>
Signed-off-by: Leon Alrae <address@hidden>


  Commit: b307446e04232b3a87e9da04886895a8e5a4a407
      
https://github.com/qemu/qemu/commit/b307446e04232b3a87e9da04886895a8e5a4a407
  Author: Aurelien Jarno <address@hidden>
  Date:   2015-09-18 (Fri, 18 Sep 2015)

  Changed paths:
    M target-mips/translate.c

  Log Message:
  -----------
  target-mips: get rid of MIPS_DEBUG_SIGN_EXTENSIONS

MIPS_DEBUG_SIGN_EXTENSIONS was used sometimes ago to verify that 32-bit
instructions correctly sign extend their results. It's now not need
anymore, remove it.

Cc: Leon Alrae <address@hidden>
Signed-off-by: Aurelien Jarno <address@hidden>
Reviewed-by: Leon Alrae <address@hidden>
Signed-off-by: Leon Alrae <address@hidden>


  Commit: ceb0ee147df35adc7b705da1c84a4624c9cabb21
      
https://github.com/qemu/qemu/commit/ceb0ee147df35adc7b705da1c84a4624c9cabb21
  Author: Serge Vakulenko <address@hidden>
  Date:   2015-09-18 (Fri, 18 Sep 2015)

  Changed paths:
    M hw/mips/cputimer.c

  Log Message:
  -----------
  pic32: use LCG algorithm for generated random index of TLBWR instruction

The LFSR algorithm, used for generating random TLB indexes for TLBWR
instruction, was inclined to produce a degenerate sequence in some cases.
For example, for 16-entry TLB size and Wired=1, it gives: 15, 6, 7, 2,
7, 2, 7, 2, 7, 2, 7, 2, 7, 2, 7, 2, 7, 2, 7, 2, 7, 2, 7, 2, 7, 2, 7, 2...
When replaced with LCG algorithm from ISO/IEC 9899 standard, the sequence
looks much better, with about the same computational effort needed.

Signed-off-by: Serge Vakulenko <address@hidden>
Reviewed-by: Aurelien Jarno <address@hidden>
Reviewed-by: Leon Alrae <address@hidden>
Signed-off-by: Leon Alrae <address@hidden>


  Commit: 3adafef2f35d9061b56a09071b2589b9e0b36f76
      
https://github.com/qemu/qemu/commit/3adafef2f35d9061b56a09071b2589b9e0b36f76
  Author: Leon Alrae <address@hidden>
  Date:   2015-09-18 (Fri, 18 Sep 2015)

  Changed paths:
    M hw/mips/cputimer.c

  Log Message:
  -----------
  target-mips: fix corner case in TLBWR causing QEMU to hang

cpu_mips_get_random() function is used to generate a random index from
CP0.Wired to TLBSize-1 range. Current implementation avoids generating
the same as before value, hence the while loop. If the guest sets
CP0.Wired to TLBSize-1 (which actually does not sound to be very
practical) QEMU will get stuck in the loop infinitely as we always
generate the same index.

Signed-off-by: Leon Alrae <address@hidden>
Reviewed-by: Aurelien Jarno <address@hidden>


  Commit: db77d8523909b32d798cd2c80de422b68f9e5c42
      
https://github.com/qemu/qemu/commit/db77d8523909b32d798cd2c80de422b68f9e5c42
  Author: Leon Alrae <address@hidden>
  Date:   2015-09-18 (Fri, 18 Sep 2015)

  Changed paths:
    M target-mips/translate.c

  Log Message:
  -----------
  target-mips: add missing restriction in DAUI instruction

rs cannot be the zero register, Reserved Instruction exception must be
signalled for this case.

Signed-off-by: Leon Alrae <address@hidden>
Reviewed-by: Aurelien Jarno <address@hidden>


  Commit: d54a299b83a07642c85a22bfe19b69ca4def9ec4
      
https://github.com/qemu/qemu/commit/d54a299b83a07642c85a22bfe19b69ca4def9ec4
  Author: Leon Alrae <address@hidden>
  Date:   2015-09-18 (Fri, 18 Sep 2015)

  Changed paths:
    M target-mips/translate.c

  Log Message:
  -----------
  target-mips: correct MTC0 instruction on MIPS64

MTC0 on a 64-bit processor should move entire 64-bit GPR content to CP0
register.

Signed-off-by: Leon Alrae <address@hidden>
Reviewed-by: Aurelien Jarno <address@hidden>


  Commit: 9c708c7f9fbb813a3fac02f2728e51e62f2f5ffc
      
https://github.com/qemu/qemu/commit/9c708c7f9fbb813a3fac02f2728e51e62f2f5ffc
  Author: Pavel Dovgaluk <address@hidden>
  Date:   2015-09-18 (Fri, 18 Sep 2015)

  Changed paths:
    M target-mips/cpu.h
    M target-mips/helper.h
    M target-mips/msa_helper.c
    M target-mips/op_helper.c
    M target-mips/translate.c

  Log Message:
  -----------
  target-mips: improve exception handling

This patch improves exception handling in MIPS.
Instructions generate several types of exceptions.
When exception is generated, it breaks the execution of the current
translation block. Implementation of the exceptions handling does not
correctly restore icount for the instruction which caused the exception.
In most cases icount will be decreased by the value equal to the size of
TB. This patch passes pointer to the translation block internals to the
exception handler. It allows correct restoring of the icount value.

Signed-off-by: Pavel Dovgalyuk <address@hidden>
Reviewed-by: Aurelien Jarno <address@hidden>
Reviewed-by: Leon Alrae <address@hidden>
address@hidden: avoid retranslation in linux-user SC, break lines
 which are over 80 chars, remove v3 changelog from the commit message]
Signed-off-by: Leon Alrae <address@hidden>


  Commit: 3bf1f5ec6a7ec8ee06c95bf308d213ebaa129ee0
      
https://github.com/qemu/qemu/commit/3bf1f5ec6a7ec8ee06c95bf308d213ebaa129ee0
  Author: Peter Maydell <address@hidden>
  Date:   2015-09-18 (Fri, 18 Sep 2015)

  Changed paths:
    M hw/mips/cputimer.c
    M target-mips/cpu.h
    M target-mips/helper.h
    M target-mips/msa_helper.c
    M target-mips/op_helper.c
    M target-mips/translate.c

  Log Message:
  -----------
  Merge remote-tracking branch 'remotes/lalrae/tags/mips-20150918' into staging

MIPS patches 2015-09-18

Changes:
* fixes for rdhwr, tlbwr, mtc0, recip.fmt, rsqrt.fmt and daui instructions
* removal of MIPS_DEBUG code
* use tcg_gen_extrh_i64_i32()
* improve random tlb index generation in cpu_mips_get_random()
* exception handling improvements to correctly restore icount

# gpg: Signature made Fri 18 Sep 2015 12:15:28 BST using RSA key ID 0B29DA6B
# gpg: Good signature from "Leon Alrae <address@hidden>"

* remotes/lalrae/tags/mips-20150918:
  target-mips: improve exception handling
  target-mips: correct MTC0 instruction on MIPS64
  target-mips: add missing restriction in DAUI instruction
  target-mips: fix corner case in TLBWR causing QEMU to hang
  pic32: use LCG algorithm for generated random index of TLBWR instruction
  target-mips: get rid of MIPS_DEBUG_SIGN_EXTENSIONS
  target-mips: get rid of MIPS_DEBUG
  target-mips: Fix RDHWR on CP0.Count
  target-mips: remove wrong checks for recip.fmt and rsqrt.fmt
  target-mips: Use tcg_gen_extrh_i64_i32

Signed-off-by: Peter Maydell <address@hidden>


Compare: https://github.com/qemu/qemu/compare/16a1b6e97c2a...3bf1f5ec6a7e
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