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[Qemu-commits] [qemu/qemu] b06c26: armv7m_nvic: Implement ICSR without u

From: GitHub
Subject: [Qemu-commits] [qemu/qemu] b06c26: armv7m_nvic: Implement ICSR without using internal...
Date: Tue, 08 Sep 2015 12:30:04 -0700 
  Branch: refs/heads/master
  Home:   https://github.com/qemu/qemu
  Commit: b06c262b45cf7afcf56dd0f2189ad8948b117e7d
      
https://github.com/qemu/qemu/commit/b06c262b45cf7afcf56dd0f2189ad8948b117e7d
  Author: Peter Maydell <address@hidden>
  Date:   2015-09-08 (Tue, 08 Sep 2015)

  Changed paths:
    M hw/intc/armv7m_nvic.c

  Log Message:
  -----------
  armv7m_nvic: Implement ICSR without using internal GIC state

Change the implementation of the Interrupt Control and State Register
in the v7M NVIC to not use the running_irq and last_active internal
state fields in the GIC. These fields don't correspond to state in
a real GIC and will be removed soon.
The changes to the ICSR are:
 * the VECTACTIVE field is documented as identical to the IPSR[8:0]
   field, so implement it that way
 * implement RETTOBASE via looking at the active state bits

Signed-off-by: Peter Maydell <address@hidden>
Message-id: address@hidden


  Commit: df92cfa60eef82dad112ca5c5d0239ec5ba7aac3
      
https://github.com/qemu/qemu/commit/df92cfa60eef82dad112ca5c5d0239ec5ba7aac3
  Author: Peter Maydell <address@hidden>
  Date:   2015-09-08 (Tue, 08 Sep 2015)

  Changed paths:
    M hw/intc/arm_gic.c

  Log Message:
  -----------
  hw/intc/arm_gic: Running priority is group priority, not full priority

Priority values for the GIC are divided into a "group priority"
and a "subpriority" (with the division being determined by the
binary point register). The running priority is only determined
by the group priority of the active interrupts, not the
subpriority. In particular, this means that there can't be more
than one active interrupt at any particular group priority.

Signed-off-by: Peter Maydell <address@hidden>
Message-id: address@hidden


  Commit: 51fd06e0eee8257fdcc147200796e362cf2298ea
      
https://github.com/qemu/qemu/commit/51fd06e0eee8257fdcc147200796e362cf2298ea
  Author: Peter Maydell <address@hidden>
  Date:   2015-09-08 (Tue, 08 Sep 2015)

  Changed paths:
    M hw/intc/arm_gic.c
    M hw/intc/arm_gic_common.c
    M include/hw/intc/arm_gic_common.h

  Log Message:
  -----------
  hw/intc/arm_gic: Fix handling of GICC_APR<n>, GICC_NSAPR<n> registers

A GICv2 has both GICC_APR<n> and GICC_NSAPR<n> registers, with
the latter holding the active priority bits for Group 1 interrupts
(usually Nonsecure interrupts), and the Nonsecure view of the
GICC_APR<n> is the second half of the GICC_NSAPR<n> registers.
Turn our half-hearted implementation of APR<n> into a proper
implementation of both APR<n> and NSAPR<n>:

 * Add the underlying state for NSAPR<n>
 * Make sure APR<n> aren't visible for pre-GICv2
 * Implement reading of NSAPR<n>
 * Make non-secure reads of APR<n> behave correctly
 * Implement writing to APR<n> and NSAPR<n>

Signed-off-by: Peter Maydell <address@hidden>
Message-id: address@hidden


  Commit: 72889c8a809f4c65796b98d5af6a18c92510ed86
      
https://github.com/qemu/qemu/commit/72889c8a809f4c65796b98d5af6a18c92510ed86
  Author: Peter Maydell <address@hidden>
  Date:   2015-09-08 (Tue, 08 Sep 2015)

  Changed paths:
    M hw/intc/arm_gic.c
    M hw/intc/arm_gic_common.c
    M include/hw/intc/arm_gic_common.h

  Log Message:
  -----------
  hw/intc/arm_gic: Drop running_irq and last_active arrays

The running_irq and last_active arrays represent state which
doesn't exist in a real hardware GIC. The only thing we use
them for is updating the running priority when an interrupt
is completed, but in fact we can use the active-priority
registers to do this. The running priority is always the
priority corresponding to the lowest set bit in the active
priority registers, because only one interrupt at any
particular priority can be active at once.

Signed-off-by: Peter Maydell <address@hidden>
Message-id: address@hidden


  Commit: d5523a13656fb8df902a15a9fd8bd652b85e97e0
      
https://github.com/qemu/qemu/commit/d5523a13656fb8df902a15a9fd8bd652b85e97e0
  Author: Peter Maydell <address@hidden>
  Date:   2015-09-08 (Tue, 08 Sep 2015)

  Changed paths:
    M hw/intc/arm_gic.c

  Log Message:
  -----------
  hw/intc/arm_gic: Actually set the active bits for active interrupts

Although we were correctly handling interrupts becoming active
and then inactive, we weren't actually exposing this to the guest
by setting the 'active' flag for the interrupt, so reads
of GICD_ICACTIVERn and GICD_ISACTIVERn would generally incorrectly
return zeroes. Correct this oversight.

Signed-off-by: Peter Maydell <address@hidden>
Message-id: address@hidden


  Commit: d714b8de7747f20fe42e5716d1d44f91e2b891f4
      
https://github.com/qemu/qemu/commit/d714b8de7747f20fe42e5716d1d44f91e2b891f4
  Author: Peter Crosthwaite <address@hidden>
  Date:   2015-09-08 (Tue, 08 Sep 2015)

  Changed paths:
    M include/qom/object.h
    M qom/object.c

  Log Message:
  -----------
  qom: Add recursive version of object_child_for_each

Useful for iterating through an entire QOM subtree.

Signed-off-by: Peter Crosthwaite <address@hidden>
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Edgar E. Iglesias <address@hidden>
Tested-by: Edgar E. Iglesias <address@hidden>
Message-id: address@hidden


  Commit: d8b1ae4237b5f8cf5037a7f341ff43dc02955256
      
https://github.com/qemu/qemu/commit/d8b1ae4237b5f8cf5037a7f341ff43dc02955256
  Author: Peter Maydell <address@hidden>
  Date:   2015-09-08 (Tue, 08 Sep 2015)

  Changed paths:
    M hw/arm/boot.c
    A include/hw/arm/linux-boot-if.h

  Log Message:
  -----------
  hw/arm: new interface for devices which need to behave differently for kernel 
boot

For ARM we have a little minimalist bootloader in hw/arm/boot.c which
takes the place of firmware if we're directly booting a Linux kernel.
Unfortunately a few devices need special case handling in this situation
to do the initialization which on real hardware would be done by
firmware. (In particular if we're booting a kernel in NonSecure state
then we need to make a TZ-aware GIC put all its interrupts into Group 1,
or the guest will be unable to use them.)

Create a new QOM interface which can be implemented by devices which
need to do something different from their default reset behaviour.
The callback will be called after machine initialization and before
first reset.

Suggested-by: Peter Crosthwaite <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Edgar E. Iglesias <address@hidden>
Reviewed-by: Peter Maydell <address@hidden>
Tested-by: Edgar E. Iglesias <address@hidden>
Message-id: address@hidden


  Commit: 8ff41f3995ad2d942ecafb72519c1f09cb811259
      
https://github.com/qemu/qemu/commit/8ff41f3995ad2d942ecafb72519c1f09cb811259
  Author: Peter Maydell <address@hidden>
  Date:   2015-09-08 (Tue, 08 Sep 2015)

  Changed paths:
    M hw/intc/arm_gic_common.c
    M include/hw/intc/arm_gic_common.h

  Log Message:
  -----------
  hw/intc/arm_gic_common: Configure IRQs as NS if doing direct NS kernel boot

If we directly boot a kernel in NonSecure on a system where the GIC
supports the security extensions then we must cause the GIC to
configure its interrupts into group 1 (NonSecure) rather than the
usual group 0, and with their initial priority set to the highest
NonSecure priority rather than the usual highest Secure priority.
Otherwise the guest kernel will be unable to use any interrupts.

Implement this behaviour, controlled by a flag which we set if
appropriate when the ARM bootloader code calls our ARMLinuxBootIf
interface callback.

Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Peter Crosthwaite <address@hidden>
Reviewed-by: Peter Maydell <address@hidden>
Reviewed-by: Edgar E. Iglesias <address@hidden>
Tested-by: Edgar E. Iglesias <address@hidden>
Message-id: address@hidden


  Commit: 4182bbb19d2e266dde0d4ed32e85e1b1be79bc61
      
https://github.com/qemu/qemu/commit/4182bbb19d2e266dde0d4ed32e85e1b1be79bc61
  Author: Peter Maydell <address@hidden>
  Date:   2015-09-08 (Tue, 08 Sep 2015)

  Changed paths:
    M hw/cpu/a15mpcore.c
    M hw/cpu/a9mpcore.c

  Log Message:
  -----------
  hw/cpu/{a15mpcore, a9mpcore}: enable TrustZone in GIC if it is enabled in CPUs

If the A9 and A15 CPUs which we're creating the peripherals for have
TrustZone (EL3) enabled, then also enable it in the GIC we create.

Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Peter Crosthwaite <address@hidden>
Reviewed-by: Peter Maydell <address@hidden>
Reviewed-by: Edgar E. Iglesias <address@hidden>
Tested-by: Edgar E. Iglesias <address@hidden>
Message-id: address@hidden


  Commit: 2d710006a0da4a9b7ddf5c02d072e178906d0ef6
      
https://github.com/qemu/qemu/commit/2d710006a0da4a9b7ddf5c02d072e178906d0ef6
  Author: Peter Maydell <address@hidden>
  Date:   2015-09-08 (Tue, 08 Sep 2015)

  Changed paths:
    M hw/arm/virt.c

  Log Message:
  -----------
  hw/arm/virt: Default to not providing TrustZone support

Switch the default for the 'virt' board to not providing TrustZone
support in either the CPU or the GIC. This is primarily for the
benefit of UEFI, which currently assumes there is no TrustZone
support, and does not set the GIC up correctly if it is TZ-aware.
It also means the board is consistent about its behaviour whether
we're using KVM or TCG (KVM never has TrustZone support).

If TrustZone support is required (for instance for running test
suites or TZ-aware firmware) it can be enabled with the
"-machine secure=on" command line option.

Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Peter Crosthwaite <address@hidden>
Reviewed-by: Peter Maydell <address@hidden>
Reviewed-by: Edgar E. Iglesias <address@hidden>
Tested-by: Edgar E. Iglesias <address@hidden>
Message-id: address@hidden


  Commit: 0e21f183ca2d000bbda1fb63959a3d41a1c3ff42
      
https://github.com/qemu/qemu/commit/0e21f183ca2d000bbda1fb63959a3d41a1c3ff42
  Author: Peter Maydell <address@hidden>
  Date:   2015-09-08 (Tue, 08 Sep 2015)

  Changed paths:
    M hw/arm/virt.c

  Log Message:
  -----------
  hw/arm/virt: Enable TZ extensions on the GIC if we are using them

If we're creating a board with support for TrustZone, then enable
it on the GIC model as well as on the CPUs.

Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Peter Crosthwaite <address@hidden>
Reviewed-by: Peter Maydell <address@hidden>
Reviewed-by: Edgar E. Iglesias <address@hidden>
Tested-by: Edgar E. Iglesias <address@hidden>
Message-id: address@hidden


  Commit: cef9ee706792b1e205fe472b67053a0e82cd058e
      
https://github.com/qemu/qemu/commit/cef9ee706792b1e205fe472b67053a0e82cd058e
  Author: Sergey Sorokin <address@hidden>
  Date:   2015-09-08 (Tue, 08 Sep 2015)

  Changed paths:
    M target-arm/translate-a64.c
    M target-arm/translate.c
    M target-arm/translate.h

  Log Message:
  -----------
  target-arm: Fix default_exception_el() function for the case when EL3 is not 
supported

If EL3 is not supported in current configuration,
we should not try to get EL3 bitness.

Signed-off-by: Sergey Sorokin <address@hidden>
Message-id: address@hidden
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>


  Commit: dbc29a868cf5b7e6fa7bb2e6c4f188b9470779c5
      
https://github.com/qemu/qemu/commit/dbc29a868cf5b7e6fa7bb2e6c4f188b9470779c5
  Author: Edgar E. Iglesias <address@hidden>
  Date:   2015-09-08 (Tue, 08 Sep 2015)

  Changed paths:
    M target-arm/helper-a64.c

  Log Message:
  -----------
  target-arm: Log the target EL when taking exceptions

Log the target EL when taking exceptions. This is useful when
debugging guest SW or QEMU itself while transitioning through
the various ELs.

Signed-off-by: Edgar E. Iglesias <address@hidden>
Reviewed-by: Alistair Francis <address@hidden>
Message-id: address@hidden
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 7a379c7e68f1b2286602b0beeeb58dcef7c9e760
      
https://github.com/qemu/qemu/commit/7a379c7e68f1b2286602b0beeeb58dcef7c9e760
  Author: Edgar E. Iglesias <address@hidden>
  Date:   2015-09-08 (Tue, 08 Sep 2015)

  Changed paths:
    M target-arm/helper.c

  Log Message:
  -----------
  target-arm: Correct opc1 for AT_S12Exx

Signed-off-by: Edgar E. Iglesias <address@hidden>
Reviewed-by: Alistair Francis <address@hidden>
Message-id: address@hidden
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>


  Commit: c96fc9b52d0a318d8026a0bcaba204d319ad91e0
      
https://github.com/qemu/qemu/commit/c96fc9b52d0a318d8026a0bcaba204d319ad91e0
  Author: Edgar E. Iglesias <address@hidden>
  Date:   2015-09-08 (Tue, 08 Sep 2015)

  Changed paths:
    M target-arm/helper.c

  Log Message:
  -----------
  target-arm: Add AArch64 access to PAR_EL1

Signed-off-by: Edgar E. Iglesias <address@hidden>
Reviewed-by: Alistair Francis <address@hidden>
Message-id: address@hidden
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 7777b7a0ba27696ddf34a19818be17cc415551cc
      
https://github.com/qemu/qemu/commit/7777b7a0ba27696ddf34a19818be17cc415551cc
  Author: Alistair Francis <address@hidden>
  Date:   2015-09-08 (Tue, 08 Sep 2015)

  Changed paths:
    M hw/net/cadence_gem.c

  Log Message:
  -----------
  cadence_gem: Correct Marvell PHY SPCFC reset value

Bit 15 of the PHY Specific Status Register is reserved and
should remain 0. Fix the reset value to ensure that the 15th
bit is not set.

Signed-off-by: Alistair Francis <address@hidden>
Reviewed-by: Edgar E. Iglesias <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 5ea8b9c5a3e823d1446a7e67d6d3b8d86bfd33d8
      
https://github.com/qemu/qemu/commit/5ea8b9c5a3e823d1446a7e67d6d3b8d86bfd33d8
  Author: Alistair Francis <address@hidden>
  Date:   2015-09-08 (Tue, 08 Sep 2015)

  Changed paths:
    M hw/ide/ahci.c
    M hw/ide/ahci.h

  Log Message:
  -----------
  ahci: Separate the AHCI state structure into the header

Pull the AHCI state structure out into the header. This allows
other containers to access the struct. This is required to add
the device to modern SoC containers.

Signed-off-by: Alistair Francis <address@hidden>
Reviewed-by: Sai Pavan Boddu <address@hidden>
Reviewed-by: Peter Crosthwaite <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>


  Commit: bb639f829f139ddc83325b3b6825f93096ee44f1
      
https://github.com/qemu/qemu/commit/bb639f829f139ddc83325b3b6825f93096ee44f1
  Author: Alistair Francis <address@hidden>
  Date:   2015-09-08 (Tue, 08 Sep 2015)

  Changed paths:
    M hw/ide/ahci.c
    M hw/ide/ahci.h

  Log Message:
  -----------
  ahci.c: Don't assume AHCIState's parent is AHCIPCIState

The AHCIState struct can either have AHCIPCIState or SysbusAHCIState
as a parent. The ahci_irq_lower() and ahci_irq_raise() functions
assume that it is always AHCIPCIState, which is not always the
case, which causes a seg fault. Verify what the container of AHCIState
is before setting the PCIDevice struct.

Signed-off-by: Alistair Francis <address@hidden>
Acked-by: John Snow <address@hidden>
Reviewed-by: Peter Crosthwaite <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>


  Commit: e1292517103f7ad6a8dc9f0795d170a78ed408a8
      
https://github.com/qemu/qemu/commit/e1292517103f7ad6a8dc9f0795d170a78ed408a8
  Author: Alistair Francis <address@hidden>
  Date:   2015-09-08 (Tue, 08 Sep 2015)

  Changed paths:
    M hw/arm/xlnx-zynqmp.c

  Log Message:
  -----------
  xlnx-zynqmp.c: Convert some of the error_propagate() calls to error_abort

Convert all of the non-realize error_propagate() calls into error_abort
calls as they shouldn't be user visible failure cases.

Signed-off-by: Alistair Francis <address@hidden>
Reviewed-by: Peter Crosthwaite <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 6fdf3282d16e7fb6e798824fb5f4f60c6a73067d
      
https://github.com/qemu/qemu/commit/6fdf3282d16e7fb6e798824fb5f4f60c6a73067d
  Author: Alistair Francis <address@hidden>
  Date:   2015-09-08 (Tue, 08 Sep 2015)

  Changed paths:
    M hw/arm/xlnx-zynqmp.c
    M include/hw/arm/xlnx-zynqmp.h

  Log Message:
  -----------
  xlnx-zynqmp: Connect the sysbus AHCI to ZynqMP

Connect the Sysbus AHCI device to ZynqMP.

Signed-off-by: Alistair Francis <address@hidden>
Reviewed-by: Sai Pavan Boddu <address@hidden>
[PMM: removed unnecessary brackets in error_propagate call]
Signed-off-by: Peter Maydell <address@hidden>


  Commit: fc04a730b7e60f4a62d6260d4eb9c537d1d3643f
      
https://github.com/qemu/qemu/commit/fc04a730b7e60f4a62d6260d4eb9c537d1d3643f
  Author: Peter Maydell <address@hidden>
  Date:   2015-09-08 (Tue, 08 Sep 2015)

  Changed paths:
    M hw/arm/boot.c
    M hw/arm/virt.c
    M hw/arm/xlnx-zynqmp.c
    M hw/cpu/a15mpcore.c
    M hw/cpu/a9mpcore.c
    M hw/ide/ahci.c
    M hw/ide/ahci.h
    M hw/intc/arm_gic.c
    M hw/intc/arm_gic_common.c
    M hw/intc/armv7m_nvic.c
    M hw/net/cadence_gem.c
    A include/hw/arm/linux-boot-if.h
    M include/hw/arm/xlnx-zynqmp.h
    M include/hw/intc/arm_gic_common.h
    M include/qom/object.h
    M qom/object.c
    M target-arm/helper-a64.c
    M target-arm/helper.c
    M target-arm/translate-a64.c
    M target-arm/translate.c
    M target-arm/translate.h

  Log Message:
  -----------
  Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20150908' 
into staging

target-arm queue:
 * Implement priority handling properly via GICC_APR
 * Enable TZ extensions on the GIC if we're using them
 * Minor preparatory patches for EL3 support
 * cadence_gem: Correct Marvell PHY SPCFC reset value
 * Support AHCI in ZynqMP

# gpg: Signature made Tue 08 Sep 2015 17:48:33 BST using RSA key ID 14360CDE
# gpg: Good signature from "Peter Maydell <address@hidden>"
# gpg:                 aka "Peter Maydell <address@hidden>"
# gpg:                 aka "Peter Maydell <address@hidden>"

* remotes/pmaydell/tags/pull-target-arm-20150908:
  xlnx-zynqmp: Connect the sysbus AHCI to ZynqMP
  xlnx-zynqmp.c: Convert some of the error_propagate() calls to error_abort
  ahci.c: Don't assume AHCIState's parent is AHCIPCIState
  ahci: Separate the AHCI state structure into the header
  cadence_gem: Correct Marvell PHY SPCFC reset value
  target-arm: Add AArch64 access to PAR_EL1
  target-arm: Correct opc1 for AT_S12Exx
  target-arm: Log the target EL when taking exceptions
  target-arm: Fix default_exception_el() function for the case when EL3 is not 
supported
  hw/arm/virt: Enable TZ extensions on the GIC if we are using them
  hw/arm/virt: Default to not providing TrustZone support
  hw/cpu/{a15mpcore, a9mpcore}: enable TrustZone in GIC if it is enabled in CPUs
  hw/intc/arm_gic_common: Configure IRQs as NS if doing direct NS kernel boot
  hw/arm: new interface for devices which need to behave differently for kernel 
boot
  qom: Add recursive version of object_child_for_each
  hw/intc/arm_gic: Actually set the active bits for active interrupts
  hw/intc/arm_gic: Drop running_irq and last_active arrays
  hw/intc/arm_gic: Fix handling of GICC_APR<n>, GICC_NSAPR<n> registers
  hw/intc/arm_gic: Running priority is group priority, not full priority
  armv7m_nvic: Implement ICSR without using internal GIC state

Signed-off-by: Peter Maydell <address@hidden>


Compare: https://github.com/qemu/qemu/compare/861128050511...fc04a730b7e6
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