[Qemu-commits] [qemu/qemu] 6675d7: xlnx-zynqmp: Connect the four OCM ban

qemu-commits
[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[Qemu-commits] [qemu/qemu] 6675d7: xlnx-zynqmp: Connect the four OCM ban

From:	GitHub
Subject:	[Qemu-commits] [qemu/qemu] 6675d7: xlnx-zynqmp: Connect the four OCM banks
Date:	Tue, 25 Aug 2015 10:30:04 -0700
  Branch: refs/heads/master
  Home:   https://github.com/qemu/qemu
  Commit: 6675d719154969456e841a7e1729c0dc14113a44
      
https://github.com/qemu/qemu/commit/6675d719154969456e841a7e1729c0dc14113a44
  Author: Alistair Francis <address@hidden>
  Date:   2015-08-25 (Tue, 25 Aug 2015)

  Changed paths:
    M hw/arm/xlnx-zynqmp.c
    M include/hw/arm/xlnx-zynqmp.h

  Log Message:
  -----------
  xlnx-zynqmp: Connect the four OCM banks

The Xilinx EP108 has four separate OCM banks which are located
adjacent to each other. This patch adds the four banks to
the ZynqMP SoC.

Signed-off-by: Alistair Francis <address@hidden>
Reviewed-by: Peter Crosthwaite <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 4b46ba6145c4c9b79641efdcc9f1aa92fdbf779c
      
https://github.com/qemu/qemu/commit/4b46ba6145c4c9b79641efdcc9f1aa92fdbf779c
  Author: Alistair Francis <address@hidden>
  Date:   2015-08-25 (Tue, 25 Aug 2015)

  Changed paths:
    M MAINTAINERS

  Log Message:
  -----------
  MAINTAINERS: Update Xilinx Maintainership

Peter C is leaving Xilinx, so update the maintainer list
to point to Alistair and Edgar from Xilinx and Peter's
personal email address.

Signed-off-by: Alistair Francis <address@hidden>
Reviewed-by: Peter Crosthwaite <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 137805f5d8504933faa4fe129cdab88f2695a8c2
      
https://github.com/qemu/qemu/commit/137805f5d8504933faa4fe129cdab88f2695a8c2
  Author: Alistair Francis <address@hidden>
  Date:   2015-08-25 (Tue, 25 Aug 2015)

  Changed paths:
    M MAINTAINERS

  Log Message:
  -----------
  MAINTAINERS: Add ZynqMP to MAINTAINERS file

Add the Xilinx ZynqMP SoC and EP108 machine to the maintainers
file.

Signed-off-by: Alistair Francis <address@hidden>
Reviewed-by: Peter Crosthwaite <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 4cfb8ad896a6f85953038bd913ce3d82d347013d
      
https://github.com/qemu/qemu/commit/4cfb8ad896a6f85953038bd913ce3d82d347013d
  Author: Peter Maydell <address@hidden>
  Date:   2015-08-25 (Tue, 25 Aug 2015)

  Changed paths:
    M target-arm/helper.c

  Log Message:
  -----------
  target-arm: Add missing MAIR_EL3 and TPIDR_EL3 registers

Add the AArch64 registers MAIR_EL3 and TPIDR_EL3, which are the only
two which we had implemented the 32-bit Secure equivalents of but
not the 64-bit Secure versions.

Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Edgar E. Iglesias <address@hidden>
Message-id: address@hidden


  Commit: 2179ef958c81480b841ffa0aab5e265688ffd2b0
      
https://github.com/qemu/qemu/commit/2179ef958c81480b841ffa0aab5e265688ffd2b0
  Author: Peter Maydell <address@hidden>
  Date:   2015-08-25 (Tue, 25 Aug 2015)

  Changed paths:
    M target-arm/helper.c

  Log Message:
  -----------
  target-arm: Implement missing AMAIR registers

The AMAIR registers are for providing auxiliary implementation
defined memory attributes. We already implemented a RAZ/WI
AMAIR_EL1; add the EL2 and EL3 versions for consistency.

Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Edgar E. Iglesias <address@hidden>
Message-id: address@hidden


  Commit: 37cd6c2478196623ca28526627ca8c69afe0d654
      
https://github.com/qemu/qemu/commit/37cd6c2478196623ca28526627ca8c69afe0d654
  Author: Peter Maydell <address@hidden>
  Date:   2015-08-25 (Tue, 25 Aug 2015)

  Changed paths:
    M target-arm/helper.c

  Log Message:
  -----------
  target-arm: Implement missing AFSR registers

The AFSR registers are implementation dependent auxiliary fault
status registers. We already implemented a RAZ/WI AFSR0_EL1 and
AFSR_EL1; add the missing AFSR{0,1}_EL{2,3} for consistency.

Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Edgar E. Iglesias <address@hidden>
Message-id: address@hidden


  Commit: 834a6c6920316d39aaf0e68ac936c0a3ad164815
      
https://github.com/qemu/qemu/commit/834a6c6920316d39aaf0e68ac936c0a3ad164815
  Author: Peter Maydell <address@hidden>
  Date:   2015-08-25 (Tue, 25 Aug 2015)

  Changed paths:
    M target-arm/helper.c

  Log Message:
  -----------
  target-arm: Implement missing ACTLR registers

We already implemented ACTLR_EL1; add the missing ACTLR_EL2 and
ACTLR_EL3, for consistency.

Since we don't currently have any CPUs that need the EL2/EL3
versions to reset to non-zero values, implement as RAZ/WI.

Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Edgar E. Iglesias <address@hidden>
Message-id: address@hidden


  Commit: d0a2cbceb2aa20d64d53e1c20c7d26a78ade8382
      
https://github.com/qemu/qemu/commit/d0a2cbceb2aa20d64d53e1c20c7d26a78ade8382
  Author: Peter Maydell <address@hidden>
  Date:   2015-08-25 (Tue, 25 Aug 2015)

  Changed paths:
    M target-arm/helper.c

  Log Message:
  -----------
  target-arm: there is no TTBR1 for 32-bit EL2 stage 1 translations

For EL2 stage 1 translations, there is no TTBR1. We were already
handling this for 64-bit EL2; add the code to take the 'no TTBR1'
code path for 64-bit EL2 as well.

Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Edgar E. Iglesias <address@hidden>
Message-id: address@hidden


  Commit: 2a47df953202e1f226aa045ea974427c4540a167
      
https://github.com/qemu/qemu/commit/2a47df953202e1f226aa045ea974427c4540a167
  Author: Peter Maydell <address@hidden>
  Date:   2015-08-25 (Tue, 25 Aug 2015)

  Changed paths:
    M target-arm/helper.c

  Log Message:
  -----------
  target-arm: Wire up AArch64 EL2 and EL3 address translation ops

Wire up the AArch64 EL2 and EL3 address translation operations
(AT S12E1*, AT S12E0*, AT S1E2*, AT S1E3*), and correct some
errors in the ats_write64() function in previously unused code
that would have done the wrong kind of lookup for accesses from
EL3 when SCR.NS==0.

Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Edgar E. Iglesias <address@hidden>
Message-id: address@hidden


  Commit: e76157264da20b85698b09fa5eb8e02e515e232c
      
https://github.com/qemu/qemu/commit/e76157264da20b85698b09fa5eb8e02e515e232c
  Author: Peter Maydell <address@hidden>
  Date:   2015-08-25 (Tue, 25 Aug 2015)

  Changed paths:
    M target-arm/cpu.h
    M target-arm/op_helper.c

  Log Message:
  -----------
  target-arm: Add CP_ACCESS_TRAP_UNCATEGORIZED_EL2, 3

Some coprocessor register access functions need to be able
to report "trap to EL3 with an 'uncategorized' syndrome";
add the necessary CPAccessResult enum and handling for it.

I don't currently know of any registers that need to trap
to EL2 with the 'uncategorized' syndrome, but adding the
_EL2 enum as well is trivial and fills in what would
otherwise be an odd gap in the handling.

Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Edgar E. Iglesias <address@hidden>
Message-id: address@hidden


  Commit: 87562e4f4a2bdd028eef3549ce9cb4e7c83cb0bf
      
https://github.com/qemu/qemu/commit/87562e4f4a2bdd028eef3549ce9cb4e7c83cb0bf
  Author: Peter Maydell <address@hidden>
  Date:   2015-08-25 (Tue, 25 Aug 2015)

  Changed paths:
    M target-arm/helper.c

  Log Message:
  -----------
  target-arm: Enable the AArch32 ATS12NSO ops

Apply the correct conditions in the ats_access() function for
the ATS12NSO* address translation operations:
 * succeed at EL2 or EL3
 * normal UNDEF trap from NS EL1
 * trap to EL3 from S EL1 (only possible if EL3 is AArch64)

(This change means they're now available in our EL3-supporting
CPUs when they would previously always UNDEF.)

Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Edgar E. Iglesias <address@hidden>
Message-id: address@hidden


  Commit: 14db7fe09a2c8d561ff37f98b328409906a560d7
      
https://github.com/qemu/qemu/commit/14db7fe09a2c8d561ff37f98b328409906a560d7
  Author: Peter Maydell <address@hidden>
  Date:   2015-08-25 (Tue, 25 Aug 2015)

  Changed paths:
    M target-arm/helper.c

  Log Message:
  -----------
  target-arm: Implement AArch32 ATS1H* operations

Implement the AArch32 ATS1H* operations which perform
Hyp mode stage 1 translations.

Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Edgar E. Iglesias <address@hidden>
Message-id: address@hidden


  Commit: d7a74a9d4a68e27b3a8ceda17bb95cb0a23d8e4d
      
https://github.com/qemu/qemu/commit/d7a74a9d4a68e27b3a8ceda17bb95cb0a23d8e4d
  Author: Peter Maydell <address@hidden>
  Date:   2015-08-25 (Tue, 25 Aug 2015)

  Changed paths:
    M cputlb.c
    M include/exec/exec-all.h

  Log Message:
  -----------
  cputlb: Add functions for flushing TLB for a single MMU index

Guest CPU TLB maintenance operations may be sufficiently
specialized to only need to flush TLB entries corresponding
to a particular MMU index. Implement cputlb functions for
this, to avoid the inefficiency of flushing TLB entries
which we don't need to.

Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Edgar E. Iglesias <address@hidden>
Message-id: address@hidden


  Commit: 83ddf975777cc23337b7ef92e83b1b9c949396f3
      
https://github.com/qemu/qemu/commit/83ddf975777cc23337b7ef92e83b1b9c949396f3
  Author: Peter Maydell <address@hidden>
  Date:   2015-08-25 (Tue, 25 Aug 2015)

  Changed paths:
    M target-arm/helper.c

  Log Message:
  -----------
  target-arm: Move TLBI ALLE1/ALLE1IS definitions into numeric order

Move the two regdefs for TLBI ALLE1 and TLBI ALLE1IS down so that the
whole set of AArch64 TLBI regdefs is arranged in numeric order.

Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Edgar E. Iglesias <address@hidden>
Message-id: address@hidden


  Commit: fd3ed969227f54f08f87d9eb6de2d4e48e99279b
      
https://github.com/qemu/qemu/commit/fd3ed969227f54f08f87d9eb6de2d4e48e99279b
  Author: Peter Maydell <address@hidden>
  Date:   2015-08-25 (Tue, 25 Aug 2015)

  Changed paths:
    M target-arm/helper.c

  Log Message:
  -----------
  target-arm: Restrict AArch64 TLB flushes to the MMU indexes they must touch

Now we have the ability to flush the TLB only for specific MMU indexes,
update the AArch64 TLB maintenance instruction implementations to only
flush the parts of the TLB they need to, rather than doing full flushes.

We take the opportunity to remove some duplicate functions (the per-asid
tlb ops work like the non-per-asid ones because we don't support
flushing a TLB only by ASID) and to bring the function names in line
with the architectural TLBI operation names.

Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Edgar E. Iglesias <address@hidden>
Message-id: address@hidden


  Commit: 2bfb9d75d37ceab6ef1674f54fca06c74f6978e7
      
https://github.com/qemu/qemu/commit/2bfb9d75d37ceab6ef1674f54fca06c74f6978e7
  Author: Peter Maydell <address@hidden>
  Date:   2015-08-25 (Tue, 25 Aug 2015)

  Changed paths:
    M target-arm/helper.c

  Log Message:
  -----------
  target-arm: Implement missing EL2 TLBI operations

Implement the missing TLBI operations that exist only
if EL2 is implemented.

Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Edgar E. Iglesias <address@hidden>
Message-id: address@hidden


  Commit: 43efaa33faa2bdaed789b9ddaa76b30880e57554
      
https://github.com/qemu/qemu/commit/43efaa33faa2bdaed789b9ddaa76b30880e57554
  Author: Peter Maydell <address@hidden>
  Date:   2015-08-25 (Tue, 25 Aug 2015)

  Changed paths:
    M target-arm/helper.c

  Log Message:
  -----------
  target-arm: Implement missing EL3 TLB invalidate operations

Implement the remaining stage 1 TLB invalidate operations
visible from EL3.

Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Edgar E. Iglesias <address@hidden>
Message-id: address@hidden


  Commit: cea66e91212164e02ad1d245c2371f7e8eb59e7f
      
https://github.com/qemu/qemu/commit/cea66e91212164e02ad1d245c2371f7e8eb59e7f
  Author: Peter Maydell <address@hidden>
  Date:   2015-08-25 (Tue, 25 Aug 2015)

  Changed paths:
    M target-arm/helper.c

  Log Message:
  -----------
  target-arm: Implement AArch64 TLBI operations on IPAs

Implement the AArch64 TLBI operations which take an intermediate
physical address and invalidate stage 2 translations.

Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Edgar E. Iglesias <address@hidden>
Message-id: address@hidden


  Commit: 7df9671989c1cfa693764f9ae6349324b2ada02a
      
https://github.com/qemu/qemu/commit/7df9671989c1cfa693764f9ae6349324b2ada02a
  Author: Peter Maydell <address@hidden>
  Date:   2015-08-25 (Tue, 25 Aug 2015)

  Changed paths:
    M MAINTAINERS
    M cputlb.c
    M hw/arm/xlnx-zynqmp.c
    M include/exec/exec-all.h
    M include/hw/arm/xlnx-zynqmp.h
    M target-arm/cpu.h
    M target-arm/helper.c
    M target-arm/op_helper.c

  Log Message:
  -----------
  Merge remote-tracking branch 
'remotes/pmaydell/tags/pull-target-arm-20150825-1' into staging

target-arm queue:
 * add missing EL2/EL3 TLBI operations
 * add missing EL2/EL3 ATS operations
 * add missing EL2/EL3 registers
 * update Xilinx MAINTAINERS info
 * Xilinx: connect the four OCM banks

# gpg: Signature made Tue 25 Aug 2015 16:22:43 BST using RSA key ID 14360CDE
# gpg: Good signature from "Peter Maydell <address@hidden>"
# gpg:                 aka "Peter Maydell <address@hidden>"
# gpg:                 aka "Peter Maydell <address@hidden>"

* remotes/pmaydell/tags/pull-target-arm-20150825-1:
  target-arm: Implement AArch64 TLBI operations on IPAs
  target-arm: Implement missing EL3 TLB invalidate operations
  target-arm: Implement missing EL2 TLBI operations
  target-arm: Restrict AArch64 TLB flushes to the MMU indexes they must touch
  target-arm: Move TLBI ALLE1/ALLE1IS definitions into numeric order
  cputlb: Add functions for flushing TLB for a single MMU index
  target-arm: Implement AArch32 ATS1H* operations
  target-arm: Enable the AArch32 ATS12NSO ops
  target-arm: Add CP_ACCESS_TRAP_UNCATEGORIZED_EL2, 3
  target-arm: Wire up AArch64 EL2 and EL3 address translation ops
  target-arm: there is no TTBR1 for 32-bit EL2 stage 1 translations
  target-arm: Implement missing ACTLR registers
  target-arm: Implement missing AFSR registers
  target-arm: Implement missing AMAIR registers
  target-arm: Add missing MAIR_EL3 and TPIDR_EL3 registers
  MAINTAINERS: Add ZynqMP to MAINTAINERS file
  MAINTAINERS: Update Xilinx Maintainership
  xlnx-zynqmp: Connect the four OCM banks

Signed-off-by: Peter Maydell <address@hidden>


Compare: https://github.com/qemu/qemu/compare/34a4450434f1...7df9671989c1
[Prev in Thread]
Current Thread
[Next in Thread]
[Qemu-commits] [qemu/qemu] 6675d7: xlnx-zynqmp: Connect the four OCM banks, GitHub <=
Prev by Date: [Qemu-commits] [qemu/qemu] 29f3ff: tcg/optimize: fix constant signedness
Next by Date: [Qemu-commits] [qemu/qemu] eb8934: vnc: fix memory corruption (CVE-2015-5225)
Previous by thread: [Qemu-commits] [qemu/qemu] 29f3ff: tcg/optimize: fix constant signedness
Next by thread: [Qemu-commits] [qemu/qemu] eb8934: vnc: fix memory corruption (CVE-2015-5225)
Index(es):
- Date
- Thread