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[PATCH 2/3] hw/block/nvme: move msix table and pba to BAR 0
From: |
Klaus Jensen |
Subject: |
[PATCH 2/3] hw/block/nvme: move msix table and pba to BAR 0 |
Date: |
Mon, 23 Nov 2020 07:59:26 +0100 |
From: Klaus Jensen <k.jensen@samsung.com>
In the interest of supporting both CMB and PMR to be enabled on the same
device, move the MSI-X table and pending bit out of BAR 4 and into BAR
0.
This is a simplified version of the patch contributed by Andrzej
Jakowski (see [1]). Leaving the CMB at offset 0 removes the need for
changes to CMB address mapping code.
[1]:
https://lore.kernel.org/qemu-devel/20200729220107.37758-3-andrzej.jakowski@linux.intel.com/
Signed-off-by: Klaus Jensen <k.jensen@samsung.com>
---
hw/block/nvme.h | 1 +
hw/block/nvme.c | 24 ++++++++++++++++++++++--
2 files changed, 23 insertions(+), 2 deletions(-)
diff --git a/hw/block/nvme.h b/hw/block/nvme.h
index e080a2318a50..b7b42e70f97f 100644
--- a/hw/block/nvme.h
+++ b/hw/block/nvme.h
@@ -116,6 +116,7 @@ typedef struct NvmeFeatureVal {
typedef struct NvmeCtrl {
PCIDevice parent_obj;
+ MemoryRegion bar0;
MemoryRegion iomem;
MemoryRegion ctrl_mem;
NvmeBar bar;
diff --git a/hw/block/nvme.c b/hw/block/nvme.c
index 4c599159f533..db8c5ae2f527 100644
--- a/hw/block/nvme.c
+++ b/hw/block/nvme.c
@@ -2660,6 +2660,8 @@ static void nvme_init_pmr(NvmeCtrl *n, PCIDevice *pci_dev)
static void nvme_init_pci(NvmeCtrl *n, PCIDevice *pci_dev, Error **errp)
{
uint8_t *pci_conf = pci_dev->config;
+ uint64_t bar_size, msix_table_size, msix_pba_size;
+ unsigned msix_table_offset, msix_pba_offset;
pci_conf[PCI_INTERRUPT_PIN] = 1;
pci_config_set_prog_interface(pci_conf, 0x2);
@@ -2675,11 +2677,29 @@ static void nvme_init_pci(NvmeCtrl *n, PCIDevice
*pci_dev, Error **errp)
pci_config_set_class(pci_conf, PCI_CLASS_STORAGE_EXPRESS);
pcie_endpoint_cap_init(pci_dev, 0x80);
+ bar_size = QEMU_ALIGN_UP(n->reg_size, 4 * KiB);
+ msix_table_offset = bar_size;
+ msix_table_size = PCI_MSIX_ENTRY_SIZE * n->params.msix_qsize;
+
+ bar_size += msix_table_size;
+ bar_size = QEMU_ALIGN_UP(bar_size, 4 * KiB);
+ msix_pba_offset = bar_size;
+ msix_pba_size = QEMU_ALIGN_UP(n->params.msix_qsize, 64) / 8;
+
+ bar_size += msix_pba_size;
+ bar_size = pow2ceil(bar_size);
+
+ memory_region_init(&n->bar0, OBJECT(n), "nvme-bar0", bar_size);
memory_region_init_io(&n->iomem, OBJECT(n), &nvme_mmio_ops, n, "nvme",
n->reg_size);
+ memory_region_add_subregion(&n->bar0, 0, &n->iomem);
+
pci_register_bar(pci_dev, 0, PCI_BASE_ADDRESS_SPACE_MEMORY |
- PCI_BASE_ADDRESS_MEM_TYPE_64, &n->iomem);
- if (msix_init_exclusive_bar(pci_dev, n->params.msix_qsize, 4, errp)) {
+ PCI_BASE_ADDRESS_MEM_TYPE_64, &n->bar0);
+
+ if (msix_init(pci_dev, n->params.msix_qsize,
+ &n->bar0, 0, msix_table_offset,
+ &n->bar0, 0, msix_pba_offset, 0, errp)) {
return;
}
--
2.29.2