Re: [PATCH] hw/block/pflash_cfi01: Limit maximum flash size to 256 MiB

[Peter Maydell]

On Mon, 25 May 2020 at 16:58, Philippe Mathieu-Daudé <address@hidden> wrote:
>
> As of this commit, the biggest CFI01 NOR flash documented is
> the Micron PC28F00BP33EF. Its size is 2 GiB (256 MiB).
>
> Actually this "2Gb device employs a virtual chip enable feature,
> which combines two 1Gb die with a common chip enable".
>
> Since we do not want to model unrealistic hardware, cap the
> current model to this maximum. At least we have a datasheet
> to refer.
>
> If a bigger flash is provided, the user get this warning:
>
>   qemu-system-aarch64: Initialization of device cfi.pflash01 failed: Maximum 
> supported CFI flash size is 16 MiB.
>
> Note, the sbsa-ref ARM machine introduced in commit 64580903c2b
> already uses a pair of 256 MiB flash devices.

What problem is this check solving? Is there some implementation
imposed limitation or a limit within the flash header format
that means larger sizes don't work? If so, what's the restriction?

thanks
-- PMM