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Re: [PATCH 00/11] Various updates for the Cadence GEM model
From: |
Peter Maydell |
Subject: |
Re: [PATCH 00/11] Various updates for the Cadence GEM model |
Date: |
Fri, 27 Oct 2023 13:16:01 +0100 |
On Tue, 17 Oct 2023 at 20:44, Luc Michel <luc.michel@amd.com> wrote:
>
> Hi,
>
> This series brings small changes to the Cadence GEM Ethernet model.
> There is (almost) no behaviour change.
>
> Patches 1 to 9 replace handcrafted defines with the use of REG32 and
> FIELDS macros for register and fields declarations.
>
> Patch 10 fixes PHY accesses so that they are done only on a write to the
> PHYMNTNC register (as the real hardware does).
>
> Patch 11 fixes a potential bug on hosts where unsigned would not be 32
> bits.
Applied to target-arm.next, thanks.
Note to Sai for the future: in Reviewed-by: tags, as with
Signed-off-by: tags, the expected form is "Full Name <email@example.com>",
not just a bare email address. (I would actively ask for a change
on a signed-off-by line with an email alone, but for Reviewed-by
it's less significant.)
thanks
-- PMM
- [PATCH 04/11] hw/net/cadence_gem: use FIELD to describe NWCFG register fields, (continued)
- [PATCH 04/11] hw/net/cadence_gem: use FIELD to describe NWCFG register fields, Luc Michel, 2023/10/17
- [PATCH 07/11] hw/net/cadence_gem: use FIELD to describe IRQ register fields, Luc Michel, 2023/10/17
- [PATCH 03/11] hw/net/cadence_gem: use FIELD to describe NWCTRL register fields, Luc Michel, 2023/10/17
- [PATCH 06/11] hw/net/cadence_gem: use FIELD to describe [TX|RX]STATUS register fields, Luc Michel, 2023/10/17
- [PATCH 09/11] hw/net/cadence_gem: use FIELD to describe PHYMNTNC register fields, Luc Michel, 2023/10/17
- Re: [PATCH 00/11] Various updates for the Cadence GEM model,
Peter Maydell <=