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Re: [PATCH v4] target/arm: Add Neoverse-N1 registers
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From: |
Marcin Juszkiewicz |
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Subject: |
Re: [PATCH v4] target/arm: Add Neoverse-N1 registers |
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Date: |
Mon, 13 Mar 2023 19:31:57 +0100 |
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User-agent: |
Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.8.0 |
W dniu 13.03.2023 o 04:39, Chen Baozi pisze:
Add implementation defined registers for neoverse-n1 which
would be accessed by TF-A. Since there is no DSU in Qemu,
CPUCFR_EL1.SCU bit is set to 1 to avoid DSU registers definition.
Signed-off-by: Chen Baozi<chenbaozi@phytium.com.cn>
Tested-by: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org>
~ # cat /proc/cpuinfo
processor : 0
BogoMIPS : 125.00
Features : fp asimd evtstrm aes pmull sha1 sha2 crc32 atomics
fphp asimdhp cpuid asimdrdm lrcpc dcpop asimddp ssbs
CPU implementer : 0x41
CPU architecture: 8
CPU variant : 0x4
CPU part : 0xd0c
CPU revision : 1