Re: Help: NVIC, level-triggered interrupts and interrupt pending

[Peter Maydell]

On Thu, 2 Jun 2022 at 12:44, Igor Kotrasiński <i.kotrasinsk@samsung.com> wrote:
> I don't have a test image yet, but I'm pretty confident I understand the
> bug now.
>
> As you said, an interrupt becomes pending if the input IRQ line is high
> and the interrupt is not Active. The first condition in R_CVJS doesn't
> mention any transitions, so the "event" mentioned there happens at any
> time the condition is valid. So, no matter what writing to pending-clear
> register does, pending status should still be set afterwards. This would
> also match the explanatory document I found.

Yeah, I came to basically the same conclusion. (On real hardware
it's possible that the 'line high and not active' condition is
only re-checked on the next clock tick so it might go non-pending
for a cycle, but software wouldn't be able to see the difference.)

I want to go through the rest of the NVIC code to make sure we're
also correctly implementing this part of the rule (ie that wherever
active goes low we check if the line is high and set pending: we
do that in the exception-return codepath but might have missed it
in some other places).

thanks
-- PMM