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Re: DSB does not seem to wait for TLBI completion

From: Idan Horowitz
Subject: Re: DSB does not seem to wait for TLBI completion
Date: Sun, 21 Nov 2021 09:57:35 +0200

Peter Maydell <peter.maydell@linaro.org> wrote:
> Do you have a repro case you can give us ?
> Does your setup involve SMP, or is this all on a single CPU ?

I'll try to create a minimized reproduction case.
As for the SMP question, I'm emulating 4 threads (note that the issue
does reproduce with less threads, but extremely rarely) with icount
enabled. (so single threaded tcg)
It is a bit curious that the amount of emulated threads affects it
though, as both the mapping of the correct page, the TLB invalidation,
and the data abort all happen on the same emulated thread.

> Note that the architecture says that the DSB will guarantee the
> TLB maintenance operation to be finished for *other* processors,
> but that if you want to guarantee it to be finished for the
> processor which executed the TLBI then you must do a DSB followed
> by a "context synchronization event", eg a ISB insn, or return
> from exception. (See the v8 Arm ARM DDI0487G.b page D5-2833.)
> It sounds from your description as if a return-from-exception
> is done on the CPU that executed the TLBI, though...

Indeed, an eret is executed after the handing of the data abort in
order to return to the instruction that raised the exception.
(Adding an ISB after the TLB invalidation does not seem to affect the
issue besides slowing down execution)

> -- PMM

Idan Horowitz

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