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[PATCH for-6.1 6/6] hw/intc/armv7m_nvic: for v8.1M VECTPENDING hides S e
From: |
Peter Maydell |
Subject: |
[PATCH for-6.1 6/6] hw/intc/armv7m_nvic: for v8.1M VECTPENDING hides S exceptions from NS |
Date: |
Fri, 23 Jul 2021 17:21:46 +0100 |
In Arm v8.1M the VECTPENDING field in the ICSR has new behaviour: if
the register is accessed NonSecure and the highest priority pending
enabled exception (that would be returned in the VECTPENDING field)
targets Secure, then the VECTPENDING field must read 1 rather than
the exception number of the pending exception. Implement this.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
hw/intc/armv7m_nvic.c | 31 ++++++++++++++++++++++++-------
1 file changed, 24 insertions(+), 7 deletions(-)
diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c
index c9149a3b221..1e7ddcb94cb 100644
--- a/hw/intc/armv7m_nvic.c
+++ b/hw/intc/armv7m_nvic.c
@@ -804,6 +804,16 @@ void armv7m_nvic_acknowledge_irq(void *opaque)
nvic_irq_update(s);
}
+static bool vectpending_targets_secure(NVICState *s)
+{
+ /* Return true if s->vectpending targets Secure state */
+ if (s->vectpending_is_s_banked) {
+ return true;
+ }
+ return !exc_is_banked(s->vectpending) &&
+ exc_targets_secure(s, s->vectpending);
+}
+
void armv7m_nvic_get_pending_irq_info(void *opaque,
int *pirq, bool *ptargets_secure)
{
@@ -813,12 +823,7 @@ void armv7m_nvic_get_pending_irq_info(void *opaque,
assert(pending > ARMV7M_EXCP_RESET && pending < s->num_irq);
- if (s->vectpending_is_s_banked) {
- targets_secure = true;
- } else {
- targets_secure = !exc_is_banked(pending) &&
- exc_targets_secure(s, pending);
- }
+ targets_secure = vectpending_targets_secure(s);
trace_nvic_get_pending_irq_info(pending, targets_secure);
@@ -1039,7 +1044,19 @@ static uint32_t nvic_readl(NVICState *s, uint32_t
offset, MemTxAttrs attrs)
/* VECTACTIVE */
val = cpu->env.v7m.exception;
/* VECTPENDING */
- val |= (s->vectpending & 0x1ff) << 12;
+ if (s->vectpending) {
+ /*
+ * From v8.1M VECTPENDING must read as 1 if accessed as
+ * NonSecure and the highest priority pending and enabled
+ * exception targets Secure.
+ */
+ int vp = s->vectpending;
+ if (!attrs.secure && arm_feature(&cpu->env, ARM_FEATURE_V8_1M) &&
+ vectpending_targets_secure(s)) {
+ vp = 1;
+ }
+ val |= (vp & 0x1ff) << 12;
+ }
/* ISRPENDING - set if any external IRQ is pending */
if (nvic_isrpending(s)) {
val |= (1 << 22);
--
2.20.1
- [PATCH for-6.1 0/6] arm: Fix a handful of M-profile bugs, Peter Maydell, 2021/07/23
- [PATCH for-6.1 1/6] target/arm: Enforce that M-profile SP low 2 bits are always zero, Peter Maydell, 2021/07/23
- [PATCH for-6.1 3/6] target/arm: Report M-profile alignment faults correctly to the guest, Peter Maydell, 2021/07/23
- [PATCH for-6.1 2/6] target/arm: Add missing 'return's after calling v7m_exception_taken(), Peter Maydell, 2021/07/23
- [PATCH for-6.1 6/6] hw/intc/armv7m_nvic: for v8.1M VECTPENDING hides S exceptions from NS,
Peter Maydell <=
- [PATCH for-6.1 4/6] hw/intc/armv7m_nvic: ISCR.ISRPENDING is set for non-enabled pending interrupts, Peter Maydell, 2021/07/23
- [PATCH for-6.1 5/6] hw/intc/armv7m_nvic: Correct size of ICSR.VECTPENDING, Peter Maydell, 2021/07/23