Re: [PATCH v6 1/5] hw/dma: xlnx_csu_dma: Implement a Xilinx CSU DMA model

[Bin Meng]

Hi Edgar,

On Tue, Mar 2, 2021 at 11:19 PM Edgar E. Iglesias
<edgar.iglesias@gmail.com> wrote:
>
> On Tue, Mar 02, 2021 at 11:16:10PM +0800, Bin Meng wrote:
> > Hi Edgar,
>
> Hi Bin,
>
>
> >
> > On Tue, Mar 2, 2021 at 11:03 PM Edgar E. Iglesias
> > <edgar.iglesias@gmail.com> wrote:
> > >
> > > On Mon, Mar 01, 2021 at 09:20:07PM +0800, Bin Meng wrote:
> > > > From: Xuzhou Cheng <xuzhou.cheng@windriver.com>
> > > >
> > > > ZynqMP QSPI supports SPI transfer using DMA mode, but currently this
>
> ....
>
> > > The 3 DONE_CNT bits in R_STATUS need to be w1c so that SW can clear the 
> > > counter.
> > >
> > >             .w1c = R_STATUS_DONE_CNT_MASK,                                
> > >     \
> > >
> > >
> > > For reference, I'm attaching the complete diff I used to pass the 
> > > testsuite:
> > >
> >
> > Thanks for the review and testing. We will incorporate your diff, test
> > and send v7.
> >
> > Should we include your SoB tag for the diff?
>
> If you take the changes as from my example, you can include:
>
> Tested-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>

Great, thank you!

Regards,
Bin