[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[PATCH v2 11/28] target/arm: Use new FPCR_NZCV_MASK constant
From: |
Peter Maydell |
Subject: |
[PATCH v2 11/28] target/arm: Use new FPCR_NZCV_MASK constant |
Date: |
Thu, 19 Nov 2020 21:56:00 +0000 |
We defined a constant name for the mask of NZCV bits in the FPCR/FPSCR
in the previous commit; use it in a couple of places in existing code,
where we're masking out everything except NZCV for the "load to Rt=15
sets CPSR.NZCV" special case.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
---
target/arm/translate-vfp.c.inc | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/target/arm/translate-vfp.c.inc b/target/arm/translate-vfp.c.inc
index 6c4b7db8213..6bc327e9819 100644
--- a/target/arm/translate-vfp.c.inc
+++ b/target/arm/translate-vfp.c.inc
@@ -743,7 +743,7 @@ static bool gen_M_fp_sysreg_read(DisasContext *s, int regno,
* helper call for the "VMRS to CPSR.NZCV" insn.
*/
tmp = load_cpu_field(vfp.xregs[ARM_VFP_FPSCR]);
- tcg_gen_andi_i32(tmp, tmp, 0xf0000000);
+ tcg_gen_andi_i32(tmp, tmp, FPCR_NZCV_MASK);
storefn(s, opaque, tmp);
break;
default:
@@ -884,7 +884,7 @@ static bool trans_VMSR_VMRS(DisasContext *s, arg_VMSR_VMRS
*a)
case ARM_VFP_FPSCR:
if (a->rt == 15) {
tmp = load_cpu_field(vfp.xregs[ARM_VFP_FPSCR]);
- tcg_gen_andi_i32(tmp, tmp, 0xf0000000);
+ tcg_gen_andi_i32(tmp, tmp, FPCR_NZCV_MASK);
} else {
tmp = tcg_temp_new_i32();
gen_helper_vfp_get_fpscr(tmp, cpu_env);
--
2.20.1
- [PATCH v2 00/28] target/arm: Implement v8.1M and Cortex-M55, Peter Maydell, 2020/11/19
- [PATCH v2 02/28] target/arm: Implement v8.1M PXN extension, Peter Maydell, 2020/11/19
- [PATCH v2 03/28] target/arm: Don't clobber ID_PFR1.Security on M-profile cores, Peter Maydell, 2020/11/19
- [PATCH v2 04/28] target/arm: Implement VSCCLRM insn, Peter Maydell, 2020/11/19
- [PATCH v2 01/28] hw/intc/armv7m_nvic: Make all of system PPB range be RAZWI/BusFault, Peter Maydell, 2020/11/19
- [PATCH v2 05/28] target/arm: Implement CLRM instruction, Peter Maydell, 2020/11/19
- [PATCH v2 06/28] target/arm: Enforce M-profile VMRS/VMSR register restrictions, Peter Maydell, 2020/11/19
- [PATCH v2 07/28] target/arm: Refactor M-profile VMSR/VMRS handling, Peter Maydell, 2020/11/19
- [PATCH v2 09/28] target/arm: Implement VLDR/VSTR system register, Peter Maydell, 2020/11/19
- [PATCH v2 08/28] target/arm: Move general-use constant expanders up in translate.c, Peter Maydell, 2020/11/19
- [PATCH v2 11/28] target/arm: Use new FPCR_NZCV_MASK constant,
Peter Maydell <=
- [PATCH v2 12/28] target/arm: Factor out preserve-fp-state from full_vfp_access_check(), Peter Maydell, 2020/11/19
- [PATCH v2 10/28] target/arm: Implement M-profile FPSCR_nzcvqc, Peter Maydell, 2020/11/19
- [PATCH v2 17/28] target/arm: In v8.1M, don't set HFSR.FORCED on vector table fetch failures, Peter Maydell, 2020/11/19
- [PATCH v2 16/28] target/arm: For v8.1M, always clear R0-R3, R12, APSR, EPSR on exception entry, Peter Maydell, 2020/11/19
- [PATCH v2 13/28] target/arm: Implement FPCXT_S fp system register, Peter Maydell, 2020/11/19
- [PATCH v2 18/28] target/arm: Implement v8.1M REVIDR register, Peter Maydell, 2020/11/19
- [PATCH v2 15/28] hw/intc/armv7m_nvic: Update FPDSCR masking for v8.1M, Peter Maydell, 2020/11/19
- [PATCH v2 22/28] hw/intc/armv7m_nvic: Support v8.1M CCR.TRD bit, Peter Maydell, 2020/11/19
- [PATCH v2 19/28] target/arm: Implement new v8.1M NOCP check for exception return, Peter Maydell, 2020/11/19