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Re: [PATCH 02/15] target/arm: Implement v8.1M PXN extension
From: |
Richard Henderson |
Subject: |
Re: [PATCH 02/15] target/arm: Implement v8.1M PXN extension |
Date: |
Tue, 17 Nov 2020 11:10:04 -0800 |
User-agent: |
Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.10.0 |
On 11/16/20 8:08 AM, Peter Maydell wrote:
> In v8.1M the PXN architecture extension adds a new PXN bit to the
> MPU_RLAR registers, which forbids execution of code in the region
> from a privileged mode.
>
> This is another feature which is just in the generic "in v8.1M" set
> and has no ID register field indicating its presence.
>
> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
> ---
> target/arm/helper.c | 7 ++++++-
> 1 file changed, 6 insertions(+), 1 deletion(-)
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
r~
- [PATCH 00/15] target/arm: More v8.1M features, Peter Maydell, 2020/11/16
- [PATCH 01/15] hw/intc/armv7m_nvic: Make all of system PPB range be RAZWI/BusFault, Peter Maydell, 2020/11/16
- [PATCH 02/15] target/arm: Implement v8.1M PXN extension, Peter Maydell, 2020/11/16
- Re: [PATCH 02/15] target/arm: Implement v8.1M PXN extension,
Richard Henderson <=
- [PATCH 05/15] target/arm: Implement CLRM instruction, Peter Maydell, 2020/11/16
- [PATCH 03/15] target/arm: Don't clobber ID_PFR1.Security on M-profile cores, Peter Maydell, 2020/11/16
- [PATCH 06/15] target/arm: Enforce M-profile VMRS/VMSR register restrictions, Peter Maydell, 2020/11/16
- [PATCH 04/15] target/arm: Implement VSCCLRM insn, Peter Maydell, 2020/11/16
- [PATCH 07/15] target/arm: Refactor M-profile VMSR/VMRS handling, Peter Maydell, 2020/11/16