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Re: [PATCH v2 0/2] target/arm: Fix tlb flush page vs tbi

From: Philippe Mathieu-Daudé
Subject: Re: [PATCH v2 0/2] target/arm: Fix tlb flush page vs tbi
Date: Sat, 17 Oct 2020 11:01:07 +0200
User-agent: Mozilla/5.0 (X11; Linux x86_64; rv:78.0) Gecko/20100101 Thunderbird/78.3.1

On 10/16/20 11:07 PM, Richard Henderson wrote:
Since the FAR_ELx fix at 38d931687fa1, it is reported that
page granularity flushing is broken.

This makes sense, since TCG will record the entire virtual
address in its TLB, not simply the 56 significant bits.
With no other TCG support, the ARM backend should require
256 different page flushes to clear the virtual address of
any possible tag.

So I added a new tcg interface that allows passing the size
of the virtual address.  I thought a simple bit-count was a
cleaner interface than passing in a mask, since it means that
we couldn't be passed nonsensical masks like 0xdeadbeef.  It
also makes it easy to re-direct special cases.

Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>

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