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Re: [PATCH 07/10] target/arm: Implement v8.1M low-overhead-loop instruct
Re: [PATCH 07/10] target/arm: Implement v8.1M low-overhead-loop instructions
Tue, 13 Oct 2020 21:24:11 +0100
On Tue, 13 Oct 2020 at 18:30, Richard Henderson
> Well, the only further comment is that, in the followup, only WLS gains the IT
> block check. While I understand that's required to avoid an abort in QEMU for
> this case, all three of the insns have that case as CONSTRAINED UNPREDICTABLE.
> It might be worthwhile checking for IT in all of them, just to continue our
> normal "unpredictable raises sigill, when easy" choice.
Maybe, but there are a lot of instructions that are
unpredictable-in-an-IT-block (CPSID, CRC32B, HVC...)
and our general approach seems to have been "don't check unless
it would cause an actual problem". The only place I can find
where we do check for this case is in trans_B_cond_thumb(),
which we do for the same reason as here.
[PATCH 03/10] target/arm: Implement v8.1M conditional-select insns, Peter Maydell, 2020/10/12
[PATCH 09/10] target/arm: Implement FPSCR.LTPSIZE for M-profile LOB extension, Peter Maydell, 2020/10/12
[PATCH 05/10] target/arm: Don't allow BLX imm for M-profile, Peter Maydell, 2020/10/12
[PATCH 08/10] target/arm: Fix has_vfp/has_neon ID reg squashing for M-profile, Peter Maydell, 2020/10/12