[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[PATCH 3/7] hw/intc/bcm2835_ic: Trace GPU/CPU IRQ handlers
From: |
Philippe Mathieu-Daudé |
Subject: |
[PATCH 3/7] hw/intc/bcm2835_ic: Trace GPU/CPU IRQ handlers |
Date: |
Sun, 20 Sep 2020 19:58:21 +0200 |
Add trace events for GPU and CPU IRQs.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
hw/intc/bcm2835_ic.c | 4 +++-
hw/intc/trace-events | 4 ++++
2 files changed, 7 insertions(+), 1 deletion(-)
diff --git a/hw/intc/bcm2835_ic.c b/hw/intc/bcm2835_ic.c
index 53ab8f58810..9000d995e81 100644
--- a/hw/intc/bcm2835_ic.c
+++ b/hw/intc/bcm2835_ic.c
@@ -18,6 +18,7 @@
#include "migration/vmstate.h"
#include "qemu/log.h"
#include "qemu/module.h"
+#include "trace.h"
#define GPU_IRQS 64
#define ARM_IRQS 8
@@ -51,7 +52,6 @@ static void bcm2835_ic_update(BCM2835ICState *s)
set = (s->gpu_irq_level & s->gpu_irq_enable)
|| (s->arm_irq_level & s->arm_irq_enable);
qemu_set_irq(s->irq, set);
-
}
static void bcm2835_ic_set_gpu_irq(void *opaque, int irq, int level)
@@ -59,6 +59,7 @@ static void bcm2835_ic_set_gpu_irq(void *opaque, int irq, int
level)
BCM2835ICState *s = opaque;
assert(irq >= 0 && irq < 64);
+ trace_bcm2835_ic_set_gpu_irq(irq, level);
s->gpu_irq_level = deposit64(s->gpu_irq_level, irq, 1, level != 0);
bcm2835_ic_update(s);
}
@@ -68,6 +69,7 @@ static void bcm2835_ic_set_arm_irq(void *opaque, int irq, int
level)
BCM2835ICState *s = opaque;
assert(irq >= 0 && irq < 8);
+ trace_bcm2835_ic_set_cpu_irq(irq, level);
s->arm_irq_level = deposit32(s->arm_irq_level, irq, 1, level != 0);
bcm2835_ic_update(s);
}
diff --git a/hw/intc/trace-events b/hw/intc/trace-events
index 527c3f76cae..22782b3f089 100644
--- a/hw/intc/trace-events
+++ b/hw/intc/trace-events
@@ -199,3 +199,7 @@ nvic_sysreg_write(uint64_t addr, uint32_t value, unsigned
size) "NVIC sysreg wri
heathrow_write(uint64_t addr, unsigned int n, uint64_t value) "0x%"PRIx64" %u:
0x%"PRIx64
heathrow_read(uint64_t addr, unsigned int n, uint64_t value) "0x%"PRIx64" %u:
0x%"PRIx64
heathrow_set_irq(int num, int level) "set_irq: num=0x%02x level=%d"
+
+# bcm2835_ic.c
+bcm2835_ic_set_gpu_irq(int irq, int level) "GPU irq #%d level %d"
+bcm2835_ic_set_cpu_irq(int irq, int level) "CPU irq #%d level %d"
--
2.26.2
- [PATCH 0/7] hw/arm/raspi: Fix SYS_timer on Linux + misc changes, Philippe Mathieu-Daudé, 2020/09/20
- [PATCH 1/7] hw/arm/raspi: Define various blocks base addresses, Philippe Mathieu-Daudé, 2020/09/20
- [PATCH 2/7] hw/arm/bcm2835: Add more unimplemented peripherals, Philippe Mathieu-Daudé, 2020/09/20
- [PATCH 3/7] hw/intc/bcm2835_ic: Trace GPU/CPU IRQ handlers,
Philippe Mathieu-Daudé <=
- [PATCH 4/7] hw/timer/bcm2835: Introduce BCM2835_SYSTIMER_COUNT definition, Philippe Mathieu-Daudé, 2020/09/20
- [PATCH 5/7] hw/timer/bcm2835: Rename variable holding CTRL_STATUS register, Philippe Mathieu-Daudé, 2020/09/20
- [PATCH 6/7] hw/timer/bcm2835: Support the timer COMPARE registers, Philippe Mathieu-Daudé, 2020/09/20
- [PATCH 7/7] hw/arm/bcm2835_peripherals: Correctly wire the SYS_timer IRQs, Philippe Mathieu-Daudé, 2020/09/20
- Re: [PATCH 0/7] hw/arm/raspi: Fix SYS_timer on Linux + misc changes, no-reply, 2020/09/20
- Re: [PATCH 0/7] hw/arm/raspi: Fix SYS_timer on Linux + misc changes, no-reply, 2020/09/20