qemu-arm
[Top][All Lists]
Advanced

[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]

[PATCH 00/22] target/arm: Implement fp16 for AArch32 VFP


From: Peter Maydell
Subject: [PATCH 00/22] target/arm: Implement fp16 for AArch32 VFP
Date: Mon, 24 Aug 2020 15:29:12 +0100

This patchset implements fp16 support for AArch32 VFP.
I've included the final "turn it on in -cpu max" patch for
convenience for testing, but we shouldn't commit that until
we've also added AArch32 Neon fp16 support. (I have a patchset
for that in progress, but I still have a handful of insns still to
convert; I figured I'd send this lot out for review rather than
waiting and sending a 50-patch set that covered VFP and Neon.)

I'll send out the risu patch that adds patterns for fp16
insns in a moment.

thanks
-- PMM

Peter Maydell (22):
  target/arm: Remove local definitions of float constants
  target/arm: Use correct ID register check for aa32_fp16_arith
  target/arm: Implement VFP fp16 for VFP_BINOP operations
  target/arm: Implement VFP fp16 VMLA, VMLS, VNMLS, VNMLA, VNMUL
  target/arm: Macroify trans functions for VFMA, VFMS, VFNMA, VFNMS
  target/arm: Implement VFP fp16 for fused-multiply-add
  target/arm: Macroify uses of do_vfp_2op_sp() and do_vfp_2op_dp()
  target/arm: Implement VFP fp16 for VABS, VNEG, VSQRT
  target/arm: Implement VFP fp16 for VMOV immediate
  target/arm: Implement VFP fp16 VCMP
  target/arm: Implement VFP fp16 VLDR and VSTR
  target/arm: Implement VFP fp16 VCVT between float and integer
  target/arm: Make VFP_CONV_FIX macros take separate float type and
    float size
  target/arm: Use macros instead of open-coding fp16 conversion helpers
  target/arm: Implement VFP fp16 VCVT between float and fixed-point
  target/arm: Implement VFP vp16 VCVT-with-specified-rounding-mode
  target/arm: Implement VFP fp16 VSEL
  target/arm: Implement VFP fp16 VRINT*
  target/arm: Implement new VFP fp16 insn VINS
  target/arm: Implement new VFP fp16 insn VMOVX
  target/arm: Implement VFP fp16 VMOV between gp and halfprec registers
  target/arm: Enable FP16 in '-cpu max'

 target/arm/cpu.h               |   7 +-
 target/arm/helper.h            |  22 +
 target/arm/vfp-uncond.decode   |  27 +-
 target/arm/vfp.decode          |  34 +-
 target/arm/cpu.c               |   3 +-
 target/arm/cpu64.c             |  10 +-
 target/arm/helper-a64.c        |  11 -
 target/arm/translate-sve.c     |   4 -
 target/arm/vfp_helper.c        | 198 ++++----
 target/arm/translate-vfp.c.inc | 810 +++++++++++++++++++++++++++++----
 10 files changed, 894 insertions(+), 232 deletions(-)

-- 
2.20.1




reply via email to

[Prev in Thread] Current Thread [Next in Thread]