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[PATCH v9 36/46] target/arm: Handle TBI for sve scalar + int memory ops
From: |
Richard Henderson |
Subject: |
[PATCH v9 36/46] target/arm: Handle TBI for sve scalar + int memory ops |
Date: |
Thu, 25 Jun 2020 20:31:34 -0700 |
We still need to handle tbi for user-only when mte is inactive.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/arm/translate-a64.h | 1 +
target/arm/translate-a64.c | 2 +-
target/arm/translate-sve.c | 6 ++++--
3 files changed, 6 insertions(+), 3 deletions(-)
diff --git a/target/arm/translate-a64.h b/target/arm/translate-a64.h
index 781c441399..49e4865918 100644
--- a/target/arm/translate-a64.h
+++ b/target/arm/translate-a64.h
@@ -40,6 +40,7 @@ TCGv_ptr get_fpstatus_ptr(bool);
bool logic_imm_decode_wmask(uint64_t *result, unsigned int immn,
unsigned int imms, unsigned int immr);
bool sve_access_check(DisasContext *s);
+TCGv_i64 clean_data_tbi(DisasContext *s, TCGv_i64 addr);
TCGv_i64 gen_mte_check1(DisasContext *s, TCGv_i64 addr, bool is_write,
bool tag_checked, int log2_size);
TCGv_i64 gen_mte_checkN(DisasContext *s, TCGv_i64 addr, bool is_write,
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
index 7a3774bfda..e46c4a49e0 100644
--- a/target/arm/translate-a64.c
+++ b/target/arm/translate-a64.c
@@ -215,7 +215,7 @@ static void gen_a64_set_pc(DisasContext *s, TCGv_i64 src)
* of the write-back address.
*/
-static TCGv_i64 clean_data_tbi(DisasContext *s, TCGv_i64 addr)
+TCGv_i64 clean_data_tbi(DisasContext *s, TCGv_i64 addr)
{
TCGv_i64 clean = new_tmp_a64(s);
#ifdef CONFIG_USER_ONLY
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
index e4fbe48493..04eda9a126 100644
--- a/target/arm/translate-sve.c
+++ b/target/arm/translate-sve.c
@@ -4587,9 +4587,8 @@ static void do_mem_zpa(DisasContext *s, int zt, int pg,
TCGv_i64 addr,
* For e.g. LD4, there are not enough arguments to pass all 4
* registers as pointers, so encode the regno into the data field.
* For consistency, do this even for LD1.
- * TODO: mte_n check here while callers are updated.
*/
- if (mte_n && s->mte_active[0]) {
+ if (s->mte_active[0]) {
int msz = dtype_msz(dtype);
desc = FIELD_DP32(desc, MTEDESC, MIDX, get_mem_index(s));
@@ -4599,7 +4598,10 @@ static void do_mem_zpa(DisasContext *s, int zt, int pg,
TCGv_i64 addr,
desc = FIELD_DP32(desc, MTEDESC, ESIZE, 1 << msz);
desc = FIELD_DP32(desc, MTEDESC, TSIZE, mte_n << msz);
desc <<= SVE_MTEDESC_SHIFT;
+ } else {
+ addr = clean_data_tbi(s, addr);
}
+
desc = simd_desc(vsz, vsz, zt | desc);
t_desc = tcg_const_i32(desc);
t_pg = tcg_temp_new_ptr();
--
2.25.1
- [PATCH v9 25/46] target/arm: Implement helper_mte_check1, (continued)
- [PATCH v9 25/46] target/arm: Implement helper_mte_check1, Richard Henderson, 2020/06/25
- [PATCH v9 28/46] target/arm: Use mte_checkN for sve unpredicated loads, Richard Henderson, 2020/06/25
- [PATCH v9 29/46] target/arm: Use mte_checkN for sve unpredicated stores, Richard Henderson, 2020/06/25
- [PATCH v9 27/46] target/arm: Add helper_mte_check_zva, Richard Henderson, 2020/06/25
- [PATCH v9 30/46] target/arm: Use mte_check1 for sve LD1R, Richard Henderson, 2020/06/25
- [PATCH v9 31/46] target/arm: Tidy trans_LD1R_zpri, Richard Henderson, 2020/06/25
- [PATCH v9 32/46] target/arm: Add arm_tlb_bti_gp, Richard Henderson, 2020/06/25
- [PATCH v9 33/46] target/arm: Add mte helpers for sve scalar + int loads, Richard Henderson, 2020/06/25
- [PATCH v9 34/46] target/arm: Add mte helpers for sve scalar + int stores, Richard Henderson, 2020/06/25
- [PATCH v9 35/46] target/arm: Add mte helpers for sve scalar + int ff/nf loads, Richard Henderson, 2020/06/25
- [PATCH v9 36/46] target/arm: Handle TBI for sve scalar + int memory ops,
Richard Henderson <=
- [PATCH v9 38/46] target/arm: Complete TBI clearing for user-only for SVE, Richard Henderson, 2020/06/25
- [PATCH v9 39/46] target/arm: Implement data cache set allocation tags, Richard Henderson, 2020/06/25
- [PATCH v9 40/46] target/arm: Set PSTATE.TCO on exception entry, Richard Henderson, 2020/06/25
- [PATCH v9 37/46] target/arm: Add mte helpers for sve scatter/gather memory ops, Richard Henderson, 2020/06/25
- [PATCH v9 41/46] target/arm: Always pass cacheattr to get_phys_addr, Richard Henderson, 2020/06/25
- [PATCH v9 42/46] target/arm: Cache the Tagged bit for a page in MemTxAttrs, Richard Henderson, 2020/06/25
- [PATCH v9 43/46] target/arm: Create tagged ram when MTE is enabled, Richard Henderson, 2020/06/25
- [PATCH v9 44/46] target/arm: Add allocation tag storage for system mode, Richard Henderson, 2020/06/25