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[PATCH v8 22/45] target/arm: Move regime_tcr to internals.h
From: |
Richard Henderson |
Subject: |
[PATCH v8 22/45] target/arm: Move regime_tcr to internals.h |
Date: |
Tue, 23 Jun 2020 12:36:35 -0700 |
We will shortly need this in mte_helper.c as well.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/arm/internals.h | 9 +++++++++
target/arm/helper.c | 9 ---------
2 files changed, 9 insertions(+), 9 deletions(-)
diff --git a/target/arm/internals.h b/target/arm/internals.h
index c36fcb151b..7c9abbabc9 100644
--- a/target/arm/internals.h
+++ b/target/arm/internals.h
@@ -949,6 +949,15 @@ static inline uint32_t regime_el(CPUARMState *env,
ARMMMUIdx mmu_idx)
}
}
+/* Return the TCR controlling this translation regime */
+static inline TCR *regime_tcr(CPUARMState *env, ARMMMUIdx mmu_idx)
+{
+ if (mmu_idx == ARMMMUIdx_Stage2) {
+ return &env->cp15.vtcr_el2;
+ }
+ return &env->cp15.tcr_el[regime_el(env, mmu_idx)];
+}
+
/* Return the FSR value for a debug exception (watchpoint, hardware
* breakpoint or BKPT insn) targeting the specified exception level.
*/
diff --git a/target/arm/helper.c b/target/arm/helper.c
index d14313de66..33f902387b 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -9875,15 +9875,6 @@ static inline uint64_t regime_ttbr(CPUARMState *env,
ARMMMUIdx mmu_idx,
#endif /* !CONFIG_USER_ONLY */
-/* Return the TCR controlling this translation regime */
-static inline TCR *regime_tcr(CPUARMState *env, ARMMMUIdx mmu_idx)
-{
- if (mmu_idx == ARMMMUIdx_Stage2) {
- return &env->cp15.vtcr_el2;
- }
- return &env->cp15.tcr_el[regime_el(env, mmu_idx)];
-}
-
/* Convert a possible stage1+2 MMU index into the appropriate
* stage 1 MMU index
*/
--
2.25.1
- [PATCH v8 14/45] target/arm: Define arm_cpu_do_unaligned_access for user-only, (continued)
- [PATCH v8 14/45] target/arm: Define arm_cpu_do_unaligned_access for user-only, Richard Henderson, 2020/06/23
- [PATCH v8 16/45] target/arm: Implement the STGP instruction, Richard Henderson, 2020/06/23
- [PATCH v8 15/45] target/arm: Implement LDG, STG, ST2G instructions, Richard Henderson, 2020/06/23
- [PATCH v8 17/45] target/arm: Restrict the values of DCZID.BS under TCG, Richard Henderson, 2020/06/23
- [PATCH v8 18/45] target/arm: Simplify DC_ZVA, Richard Henderson, 2020/06/23
- [PATCH v8 19/45] target/arm: Implement the LDGM, STGM, STZGM instructions, Richard Henderson, 2020/06/23
- [PATCH v8 20/45] target/arm: Implement the access tag cache flushes, Richard Henderson, 2020/06/23
- [PATCH v8 21/45] target/arm: Move regime_el to internals.h, Richard Henderson, 2020/06/23
- [PATCH v8 22/45] target/arm: Move regime_tcr to internals.h,
Richard Henderson <=
- [PATCH v8 23/45] target/arm: Add gen_mte_check1, Richard Henderson, 2020/06/23
- [PATCH v8 24/45] target/arm: Add gen_mte_checkN, Richard Henderson, 2020/06/23
- [PATCH v8 25/45] target/arm: Implement helper_mte_check1, Richard Henderson, 2020/06/23
- [PATCH v8 26/45] target/arm: Implement helper_mte_checkN, Richard Henderson, 2020/06/23
- [PATCH v8 27/45] target/arm: Add helper_mte_check_zva, Richard Henderson, 2020/06/23
- [PATCH v8 28/45] target/arm: Use mte_checkN for sve unpredicated loads, Richard Henderson, 2020/06/23
- [PATCH v8 29/45] target/arm: Use mte_checkN for sve unpredicated stores, Richard Henderson, 2020/06/23