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[PATCH v2 006/100] target/arm: Merge do_vector2_p into do_mov_p
From: |
Richard Henderson |
Subject: |
[PATCH v2 006/100] target/arm: Merge do_vector2_p into do_mov_p |
Date: |
Wed, 17 Jun 2020 21:25:10 -0700 |
This is the only user of the function.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/arm/translate-sve.c | 19 ++++++-------------
1 file changed, 6 insertions(+), 13 deletions(-)
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
index a8d5c7421d..b649b9d0b5 100644
--- a/target/arm/translate-sve.c
+++ b/target/arm/translate-sve.c
@@ -178,18 +178,6 @@ static void do_dupi_z(DisasContext *s, int rd, uint64_t
word)
tcg_gen_gvec_dup_imm(MO_64, vec_full_reg_offset(s, rd), vsz, vsz, word);
}
-/* Invoke a vector expander on two Pregs. */
-static bool do_vector2_p(DisasContext *s, GVecGen2Fn *gvec_fn,
- int esz, int rd, int rn)
-{
- if (sve_access_check(s)) {
- unsigned psz = pred_gvec_reg_size(s);
- gvec_fn(esz, pred_full_reg_offset(s, rd),
- pred_full_reg_offset(s, rn), psz, psz);
- }
- return true;
-}
-
/* Invoke a vector expander on three Pregs. */
static bool do_vector3_p(DisasContext *s, GVecGen3Fn *gvec_fn,
int esz, int rd, int rn, int rm)
@@ -221,7 +209,12 @@ static bool do_vecop4_p(DisasContext *s, const GVecGen4
*gvec_op,
/* Invoke a vector move on two Pregs. */
static bool do_mov_p(DisasContext *s, int rd, int rn)
{
- return do_vector2_p(s, tcg_gen_gvec_mov, 0, rd, rn);
+ if (sve_access_check(s)) {
+ unsigned psz = pred_gvec_reg_size(s);
+ tcg_gen_gvec_mov(MO_8, pred_full_reg_offset(s, rd),
+ pred_full_reg_offset(s, rn), psz, psz);
+ }
+ return true;
}
/* Set the cpu flags as per a return from an SVE helper. */
--
2.25.1
- [PATCH v2 000/100] target/arm: Implement SVE2, Richard Henderson, 2020/06/18
- [PATCH v2 001/100] tcg: Save/restore vecop_list around minmax fallback, Richard Henderson, 2020/06/18
- [PATCH v2 003/100] target/arm: Split out gen_gvec_fn_zz, Richard Henderson, 2020/06/18
- [PATCH v2 002/100] qemu/int128: Add int128_lshift, Richard Henderson, 2020/06/18
- [PATCH v2 004/100] target/arm: Split out gen_gvec_fn_zzz, do_zzz_fn, Richard Henderson, 2020/06/18
- [PATCH v2 005/100] target/arm: Rearrange {sve, fp}_check_access assert, Richard Henderson, 2020/06/18
- [PATCH v2 006/100] target/arm: Merge do_vector2_p into do_mov_p,
Richard Henderson <=
- [PATCH v2 007/100] target/arm: Clean up 4-operand predicate expansion, Richard Henderson, 2020/06/18
- [PATCH v2 008/100] target/arm: Use tcg_gen_gvec_bitsel for trans_SEL_pppp, Richard Henderson, 2020/06/18
- [PATCH v2 009/100] target/arm: Split out gen_gvec_ool_zzzp, Richard Henderson, 2020/06/18
- [PATCH v2 011/100] target/arm: Split out gen_gvec_ool_zzp, Richard Henderson, 2020/06/18
- [PATCH v2 012/100] target/arm: Split out gen_gvec_ool_zzz, Richard Henderson, 2020/06/18
- [PATCH v2 010/100] target/arm: Merge helper_sve_clr_* and helper_sve_movz_*, Richard Henderson, 2020/06/18
- [PATCH v2 013/100] target/arm: Split out gen_gvec_ool_zz, Richard Henderson, 2020/06/18
- [PATCH v2 014/100] target/arm: Add ID_AA64ZFR0 fields and isar_feature_aa64_sve2, Richard Henderson, 2020/06/18
- [PATCH v2 016/100] target/arm: Implement SVE2 Integer Multiply - Unpredicated, Richard Henderson, 2020/06/18
- [PATCH v2 015/100] target/arm: Enable SVE2 and some extensions, Richard Henderson, 2020/06/18