Re: [PATCH 5/6] hw/arm: Add NPCM730 and NPCM750 SoC models

[Cédric Le Goater]

On 6/11/20 11:38 AM, Peter Maydell wrote:
> On Thu, 11 Jun 2020 at 07:12, Cédric Le Goater <clg@kaod.org> wrote:
>> Some don't some do. This is a bit confusing.
> 
> Probably the usual thing of people not noticing that they
> need to do something for big-endian hosts and nobody testing
> the minor platforms there.
> 
>> Peter, should we fix the boards not doing the tswap in the secondary
>> bootloader ?
> 
> Yes, we should -- it's an actual bug as well as just not being
> very consistent.
> 
>> I still have access to a PP64 BE host to test.
> 
> In an ideal world the bugs would cause "make check" and/or
> "make check-acceptance" to fail on BE hosts :-)

I gave it a try manually with an Aspeed machine and the kernel fails to boot.

Download an OpenBMC witherspoon flash image : 

  wget 
https://openpower.xyz/job/openbmc-build/lastSuccessfulBuild/distro=ubuntu,label=builder,target=witherspoon/artifact/deploy/images/witherspoon/obmc-phosphor-image-witherspoon.ubi.mtd

and run :

  qemu-system-arm -M witherspoon-bmc -nic user -drive 
file=obmc-phosphor-image-witherspoon.ubi.mtd,format=raw,if=mtd -nographic 

The kernel hangs right after activating the translation :

#ifdef CONFIG_MMU
 ARM_BE8(       orr     r0, r0, #1 << 25 )      @ big-endian page tables
                mrcne   p15, 0, r6, c2, c0, 2   @ read ttb control reg
                orrne   r0, r0, #1              @ MMU enabled
                movne   r1, #0xfffffffd         @ domain 0 = client
                bic     r6, r6, #1 << 31        @ 32-bit translation system
                bic     r6, r6, #(7 << 0) | (1 << 4)    @ use only ttbr0
                mcrne   p15, 0, r3, c2, c0, 0   @ load page table pointer
                mcrne   p15, 0, r1, c3, c0, 0   @ load domain access control
                mcrne   p15, 0, r6, c2, c0, 2   @ load ttb control
#endif
                mcr     p15, 0, r0, c7, c5, 4   @ ISB
 *there* -->    mcr     p15, 0, r0, c1, c0, 0   @ load control register
                mrc     p15, 0, r0, c1, c0, 0   @ and read it back
                mov     r0, #0
                mcr     p15, 0, r0, c7, c5, 4   @ ISB
                mov     pc, r12


C.