[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[PATCH v6 20/42] target/arm: Implement the access tag cache flushes
From: |
Richard Henderson |
Subject: |
[PATCH v6 20/42] target/arm: Implement the access tag cache flushes |
Date: |
Thu, 12 Mar 2020 12:41:57 -0700 |
Like the regular data cache flushes, these are nops within qemu.
Signed-off-by: Richard Henderson <address@hidden>
---
v6: Split out and handle el0 cache ops properly.
---
target/arm/helper.c | 65 +++++++++++++++++++++++++++++++++++++++++++++
1 file changed, 65 insertions(+)
diff --git a/target/arm/helper.c b/target/arm/helper.c
index 01d2fcf2e3..f9daeec1f4 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -6914,6 +6914,32 @@ static const ARMCPRegInfo mte_reginfo[] = {
.opc0 = 3, .opc1 = 3, .crn = 4, .crm = 2, .opc2 = 7,
.type = ARM_CP_NO_RAW,
.access = PL0_RW, .readfn = tco_read, .writefn = tco_write },
+ { .name = "DC_IGVAC", .state = ARM_CP_STATE_AA64,
+ .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 6, .opc2 = 3,
+ .type = ARM_CP_NOP, .access = PL1_W,
+ .accessfn = aa64_cacheop_poc_access },
+ { .name = "DC_IGSW", .state = ARM_CP_STATE_AA64,
+ .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 6, .opc2 = 4,
+ .type = ARM_CP_NOP, .access = PL1_W, .accessfn = access_tsw },
+ { .name = "DC_IGDVAC", .state = ARM_CP_STATE_AA64,
+ .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 6, .opc2 = 5,
+ .type = ARM_CP_NOP, .access = PL1_W,
+ .accessfn = aa64_cacheop_poc_access },
+ { .name = "DC_IGDSW", .state = ARM_CP_STATE_AA64,
+ .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 6, .opc2 = 6,
+ .type = ARM_CP_NOP, .access = PL1_W, .accessfn = access_tsw },
+ { .name = "DC_CGSW", .state = ARM_CP_STATE_AA64,
+ .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 10, .opc2 = 4,
+ .type = ARM_CP_NOP, .access = PL1_W, .accessfn = access_tsw },
+ { .name = "DC_CGDSW", .state = ARM_CP_STATE_AA64,
+ .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 10, .opc2 = 6,
+ .type = ARM_CP_NOP, .access = PL1_W, .accessfn = access_tsw },
+ { .name = "DC_CIGSW", .state = ARM_CP_STATE_AA64,
+ .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 14, .opc2 = 4,
+ .type = ARM_CP_NOP, .access = PL1_W, .accessfn = access_tsw },
+ { .name = "DC_CIGDSW", .state = ARM_CP_STATE_AA64,
+ .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 14, .opc2 = 6,
+ .type = ARM_CP_NOP, .access = PL1_W, .accessfn = access_tsw },
REGINFO_SENTINEL
};
@@ -6923,6 +6949,43 @@ static const ARMCPRegInfo mte_tco_ro_reginfo[] = {
.type = ARM_CP_CONST, .access = PL0_RW, },
REGINFO_SENTINEL
};
+
+static const ARMCPRegInfo mte_el0_cacheop_reginfo[] = {
+ { .name = "DC_CGVAC", .state = ARM_CP_STATE_AA64,
+ .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 10, .opc2 = 3,
+ .type = ARM_CP_NOP, .access = PL0_W,
+ .accessfn = aa64_cacheop_poc_access },
+ { .name = "DC_CGDVAC", .state = ARM_CP_STATE_AA64,
+ .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 10, .opc2 = 5,
+ .type = ARM_CP_NOP, .access = PL0_W,
+ .accessfn = aa64_cacheop_poc_access },
+ { .name = "DC_CGVAP", .state = ARM_CP_STATE_AA64,
+ .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 12, .opc2 = 3,
+ .type = ARM_CP_NOP, .access = PL0_W,
+ .accessfn = aa64_cacheop_poc_access },
+ { .name = "DC_CGDVAP", .state = ARM_CP_STATE_AA64,
+ .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 12, .opc2 = 5,
+ .type = ARM_CP_NOP, .access = PL0_W,
+ .accessfn = aa64_cacheop_poc_access },
+ { .name = "DC_CGVADP", .state = ARM_CP_STATE_AA64,
+ .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 13, .opc2 = 3,
+ .type = ARM_CP_NOP, .access = PL0_W,
+ .accessfn = aa64_cacheop_poc_access },
+ { .name = "DC_CGDVADP", .state = ARM_CP_STATE_AA64,
+ .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 13, .opc2 = 5,
+ .type = ARM_CP_NOP, .access = PL0_W,
+ .accessfn = aa64_cacheop_poc_access },
+ { .name = "DC_CIGVAC", .state = ARM_CP_STATE_AA64,
+ .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 14, .opc2 = 3,
+ .type = ARM_CP_NOP, .access = PL0_W,
+ .accessfn = aa64_cacheop_poc_access },
+ { .name = "DC_CIGDVAC", .state = ARM_CP_STATE_AA64,
+ .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 14, .opc2 = 5,
+ .type = ARM_CP_NOP, .access = PL0_W,
+ .accessfn = aa64_cacheop_poc_access },
+ REGINFO_SENTINEL
+};
+
#endif
static CPAccessResult access_predinv(CPUARMState *env, const ARMCPRegInfo *ri,
@@ -8048,8 +8111,10 @@ void register_cp_regs_for_features(ARMCPU *cpu)
*/
if (cpu_isar_feature(aa64_mte, cpu)) {
define_arm_cp_regs(cpu, mte_reginfo);
+ define_arm_cp_regs(cpu, mte_el0_cacheop_reginfo);
} else if (cpu_isar_feature(aa64_mte_insn_reg, cpu)) {
define_arm_cp_regs(cpu, mte_tco_ro_reginfo);
+ define_arm_cp_regs(cpu, mte_el0_cacheop_reginfo);
}
#endif
--
2.20.1
- [PATCH v6 09/42] target/arm: Implement the IRG instruction, (continued)
- [PATCH v6 09/42] target/arm: Implement the IRG instruction, Richard Henderson, 2020/03/12
- [PATCH v6 11/42] target/arm: Implement the GMI instruction, Richard Henderson, 2020/03/12
- [PATCH v6 12/42] target/arm: Implement the SUBP instruction, Richard Henderson, 2020/03/12
- [PATCH v6 08/42] target/arm: Add MTE bits to tb_flags, Richard Henderson, 2020/03/12
- [PATCH v6 10/42] target/arm: Implement the ADDG, SUBG instructions, Richard Henderson, 2020/03/12
- [PATCH v6 14/42] target/arm: Add helper_probe_access, Richard Henderson, 2020/03/12
- [PATCH v6 13/42] target/arm: Define arm_cpu_do_unaligned_access for user-only, Richard Henderson, 2020/03/12
- [PATCH v6 16/42] target/arm: Implement the STGP instruction, Richard Henderson, 2020/03/12
- [PATCH v6 15/42] target/arm: Implement LDG, STG, ST2G instructions, Richard Henderson, 2020/03/12
- [PATCH v6 17/42] target/arm: Restrict the values of DCZID.BS under TCG, Richard Henderson, 2020/03/12
- [PATCH v6 20/42] target/arm: Implement the access tag cache flushes,
Richard Henderson <=
- [PATCH v6 21/42] target/arm: Move regime_el to internals.h, Richard Henderson, 2020/03/12
- [PATCH v6 18/42] target/arm: Simplify DC_ZVA, Richard Henderson, 2020/03/12
- [PATCH v6 22/42] target/arm: Move regime_tcr to internals.h, Richard Henderson, 2020/03/12
- [PATCH v6 19/42] target/arm: Implement the LDGM, STGM, STZGM instructions, Richard Henderson, 2020/03/12
- [PATCH v6 23/42] target/arm: Add gen_mte_check1, Richard Henderson, 2020/03/12
- [PATCH v6 24/42] target/arm: Add gen_mte_checkN, Richard Henderson, 2020/03/12
- [PATCH v6 25/42] target/arm: Implement helper_mte_check1, Richard Henderson, 2020/03/12
- [PATCH v6 26/42] target/arm: Implement helper_mte_checkN, Richard Henderson, 2020/03/12
- [PATCH v6 27/42] target/arm: Add helper_mte_check_zva, Richard Henderson, 2020/03/12
- [PATCH v6 28/42] target/arm: Use mte_checkN for sve unpredicated loads, Richard Henderson, 2020/03/12