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[PATCH v3 1/7] target/arm: Set ID_MMFR4.HPDS for aarch64_max_initfn
From: |
Richard Henderson |
Subject: |
[PATCH v3 1/7] target/arm: Set ID_MMFR4.HPDS for aarch64_max_initfn |
Date: |
Tue, 18 Feb 2020 11:09:52 -0800 |
We had set this for aarch32-only in arm_max_initfn, but
failed to set the same bit for aarch64.
Signed-off-by: Richard Henderson <address@hidden>
---
target/arm/cpu64.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
index 32cf8ee98b..32c3e24a3d 100644
--- a/target/arm/cpu64.c
+++ b/target/arm/cpu64.c
@@ -704,6 +704,7 @@ static void aarch64_max_initfn(Object *obj)
cpu->isar.id_mmfr3 = u;
u = cpu->isar.id_mmfr4;
+ u = FIELD_DP32(u, ID_MMFR4, HPDS, 1); /* AA32HPD */
u = FIELD_DP32(u, ID_MMFR4, AC2, 1); /* ACTLR2, HACTLR2 implemented */
cpu->isar.id_mmfr4 = u;
--
2.20.1
- [PATCH v3 0/7] target/arm: Honor more HCR_EL2 traps, Richard Henderson, 2020/02/18
- [PATCH v3 1/7] target/arm: Set ID_MMFR4.HPDS for aarch64_max_initfn,
Richard Henderson <=
- [PATCH v3 3/7] target/arm: Honor the HCR_EL2.TSW bit, Richard Henderson, 2020/02/18
- [PATCH v3 2/7] target/arm: Honor the HCR_EL2.{TVM,TRVM} bits, Richard Henderson, 2020/02/18
- [PATCH v3 4/7] target/arm: Honor the HCR_EL2.TACR bit, Richard Henderson, 2020/02/18
- [PATCH v3 6/7] target/arm: Honor the HCR_EL2.TPU bit, Richard Henderson, 2020/02/18
- [PATCH v3 5/7] target/arm: Honor the HCR_EL2.TPCP bit, Richard Henderson, 2020/02/18