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[PATCH v2 17/21] target/arm: Correct handling of PMCR_EL0.LC bit
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From: |
Peter Maydell |
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Subject: |
[PATCH v2 17/21] target/arm: Correct handling of PMCR_EL0.LC bit |
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Date: |
Fri, 14 Feb 2020 17:51:12 +0000 |
The LC bit in the PMCR_EL0 register is supposed to be:
* read/write
* RES1 on an AArch64-only implementation
* an architecturally UNKNOWN value on reset
(and use of LC==0 by software is deprecated).
We were implementing it incorrectly as read-only always zero,
though we do have all the code needed to test it and behave
accordingly.
Instead make it a read-write bit which resets to 1 always, which
satisfies all the architectural requirements above.
Reviewed-by: Richard Henderson <address@hidden>
Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>
---
target/arm/helper.c | 13 +++++++++----
1 file changed, 9 insertions(+), 4 deletions(-)
diff --git a/target/arm/helper.c b/target/arm/helper.c
index 2ebfa6c6545..468e4e89848 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -1023,6 +1023,11 @@ static const ARMCPRegInfo v6_cp_reginfo[] = {
#define PMCRC 0x4
#define PMCRP 0x2
#define PMCRE 0x1
+/*
+ * Mask of PMCR bits writeable by guest (not including WO bits like C, P,
+ * which can be written as 1 to trigger behaviour but which stay RAZ).
+ */
+#define PMCR_WRITEABLE_MASK (PMCRLC | PMCRDP | PMCRX | PMCRD | PMCRE)
#define PMXEVTYPER_P 0x80000000
#define PMXEVTYPER_U 0x40000000
@@ -1577,9 +1582,8 @@ static void pmcr_write(CPUARMState *env, const
ARMCPRegInfo *ri,
}
}
- /* only the DP, X, D and E bits are writable */
- env->cp15.c9_pmcr &= ~0x39;
- env->cp15.c9_pmcr |= (value & 0x39);
+ env->cp15.c9_pmcr &= ~PMCR_WRITEABLE_MASK;
+ env->cp15.c9_pmcr |= (value & PMCR_WRITEABLE_MASK);
pmu_op_finish(env);
}
@@ -6370,7 +6374,8 @@ static void define_pmu_regs(ARMCPU *cpu)
.access = PL0_RW, .accessfn = pmreg_access,
.type = ARM_CP_IO,
.fieldoffset = offsetof(CPUARMState, cp15.c9_pmcr),
- .resetvalue = (cpu->midr & 0xff000000) | (pmcrn << PMCRN_SHIFT),
+ .resetvalue = (cpu->midr & 0xff000000) | (pmcrn << PMCRN_SHIFT) |
+ PMCRLC,
.writefn = pmcr_write, .raw_writefn = raw_write,
};
define_one_arm_cp_reg(cpu, &pmcr);
--
2.20.1
- Re: [PATCH v2 12/21] target/arm: Read debug-related ID registers from KVM, (continued)
- [PATCH v2 09/21] target/arm: Add _aa64_ and _any_ versions of pmu_8_1 isar checks, Peter Maydell, 2020/02/14
- [PATCH v2 10/21] target/arm: Stop assuming DBGDIDR always exists, Peter Maydell, 2020/02/14
- [PATCH v2 11/21] target/arm: Move DBGDIDR into ARMISARegisters, Peter Maydell, 2020/02/14
- [PATCH v2 13/21] target/arm: Implement ARMv8.1-PMU extension, Peter Maydell, 2020/02/14
- [PATCH v2 14/21] target/arm: Implement ARMv8.4-PMU extension, Peter Maydell, 2020/02/14
- [PATCH v2 15/21] target/arm: Provide ARMv8.4-PMU in '-cpu max', Peter Maydell, 2020/02/14
- [PATCH v2 16/21] target/arm: Correct definition of PMCRDP, Peter Maydell, 2020/02/14
- [PATCH v2 17/21] target/arm: Correct handling of PMCR_EL0.LC bit,
Peter Maydell <=
- [PATCH v2 19/21] target/arm: Use isar_feature function for testing AA32HPD feature, Peter Maydell, 2020/02/14
- [PATCH v2 20/21] target/arm: Use FIELD_EX32 for testing 32-bit fields, Peter Maydell, 2020/02/14
- [PATCH v2 18/21] target/arm: Test correct register in aa32_pan and aa32_ats1e1 checks, Peter Maydell, 2020/02/14
- [PATCH v2 21/21] target/arm: Correctly implement ACTLR2, HACTLR2, Peter Maydell, 2020/02/14