Re: [PATCH] net/cadence_gem: Set PHY autonegotiation restart status

[Linus Ziegert]

Am Mo., 4. Nov. 2019 um 23:50 Uhr schrieb Alistair Francis <address@hidden>:
>
> On Mon, Nov 4, 2019 at 2:02 PM <address@hidden> wrote:
> >
> > From: Linus Ziegert <address@hidden>
> >
> > The Linux kernel PHY driver sets AN_RESTART in the BMCR of the
> > PHY when autonegotiation is started.
> > Recently the kernel started to read back the PHY's AN_RESTART
> > bit and now checks whether the autonegotiation is complete and
> > the bit was cleared [1]. Otherwise the link status is down.
> >
> > The emulated PHY needs to clear AN_RESTART immediately to inform
> > the kernel driver about the completion of autonegotiation phase.
> >
> > [1] https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=c36757eb9dee
> >
> > Signed-off-by: Linus Ziegert <address@hidden>
>
> Reviewed-by: Alistair Francis <address@hidden>

I consider this stable material. Applies cleanly to all versions starting from v1.5.0.

Thanks

 
>
> Alistair
>
> > ---
> >  hw/net/cadence_gem.c | 9 +++++----
> >  1 file changed, 5 insertions(+), 4 deletions(-)
> >
> > diff --git a/hw/net/cadence_gem.c b/hw/net/cadence_gem.c
> > index 7f9cb5ab95..b8be73dc55 100644
> > --- a/hw/net/cadence_gem.c
> > +++ b/hw/net/cadence_gem.c
> > @@ -271,9 +271,10 @@
> >  #define PHY_REG_EXT_PHYSPCFC_ST   27
> >  #define PHY_REG_CABLE_DIAG   28
> >
> > -#define PHY_REG_CONTROL_RST  0x8000
> > -#define PHY_REG_CONTROL_LOOP 0x4000
> > -#define PHY_REG_CONTROL_ANEG 0x1000
> > +#define PHY_REG_CONTROL_RST       0x8000
> > +#define PHY_REG_CONTROL_LOOP      0x4000
> > +#define PHY_REG_CONTROL_ANEG      0x1000
> > +#define PHY_REG_CONTROL_ANRESTART 0x0200
> >
> >  #define PHY_REG_STATUS_LINK     0x0004
> >  #define PHY_REG_STATUS_ANEGCMPL 0x0020
> > @@ -1345,7 +1346,7 @@ static void gem_phy_write(CadenceGEMState *s, unsigned reg_num, uint16_t val)
> >          }
> >          if (val & PHY_REG_CONTROL_ANEG) {
> >              /* Complete autonegotiation immediately */
> > -            val &= ~PHY_REG_CONTROL_ANEG;
> > +            val &= ~(PHY_REG_CONTROL_ANEG | PHY_REG_CONTROL_ANRESTART);
> >              s->phy_regs[PHY_REG_STATUS] |= PHY_REG_STATUS_ANEGCMPL;
> >          }
> >          if (val & PHY_REG_CONTROL_LOOP) {
> > --
> > 2.21.0
> >
> >