Re: [PATCH 1/5] aspeed/i2c: Add support for pool buffer transfers

[Joel Stanley]

On Wed, 16 Oct 2019 at 08:50, Cédric Le Goater <address@hidden> wrote:
>
> The Aspeed I2C controller can operate in different transfer modes :
>
>   - Byte Buffer mode, using a dedicated register to transfer a
>     byte. This is what the model supports today.
>
>   - Pool Buffer mode, using an internal SRAM to transfer multiple
>     bytes in the same command sequence.
>
> Each SoC has different SRAM characteristics. On the AST2400, 2048
> bytes of SRAM are available at offset 0x800 of the controller AHB
> window. The pool buffer can be configured from 1 to 256 bytes per bus.
>
> On the AST2500, the SRAM is at offset 0x200 and the pool buffer is of
> 16 bytes per bus.
>
> On the AST2600, the SRAM is at offset 0xC00 and the pool buffer is of
> 32 bytes per bus. It can be splitted in two for TX and RX but the
> current model does not add support for it as it it unused by known
> drivers.
>
> Signed-off-by: Cédric Le Goater <address@hidden>

Reviewed-by: Joel Stanley <address@hidden>