Re: [PATCH v2 10/16] tests/tcg: add generic version of float_convs

[Alex Bennée]

Alex Bennée <address@hidden> writes:

> Richard Henderson <address@hidden> writes:
>
>> On 9/19/19 10:10 AM, Alex Bennée wrote:
>>> This is broadly similar to the existing fcvt test for ARM but using
>>> the generic float testing framework. We should be able to pare down
>>> the ARM fcvt test case to purely half-precision with or without the
>>> Alt HP provision.
>>>
>>> Signed-off-by: Alex Bennée <address@hidden>
>>> ---
>>
>> Reviewed-by: Richard Henderson <address@hidden>
>
> This test seems to be tripping up alpha-linux-user be generating FPU
> exceptions. AFAICT we are meant to start with software exceptions
> disabled but:
>
>   cpu_alpha_store_fpcr: enabled exceptions: 2000000
>
> from the get go is what causes the eventual trip up.

I can't figure out what is meant to be going on with CONVERT_BITS. It
seems to be implying there is a direct relationship between status flags
and the exception disable bits. But that is confusing because integer
overflow (IOV) and float overflow (OVF) are different flags bit I assume
both suppressed by Overflow Disable (OVFD).

Why are we doing this magic 32 bit shuffling anyway? Is it purely to
save 32 bits of a mostly empty lower half of the FPCR register?

>
>>
>>
>> r~


--
Alex Bennée