Re: [Qemu-arm] [PATCH] target/arm: fix CBAR register for AArch64 CPUs

[Peter Maydell]

On Thu, 12 Sep 2019 at 12:01, Luc Michel <address@hidden> wrote:
>
> For AArch64 CPUs with a CBAR register, we have two views for it:
>   - in AArch64 state, the CBAR_EL1 register (S3_1_C15_C3_0), returns the
>     full 64 bits CBAR value
>   - in AArch32 state, the CBAR register (cp15, opc1=1, CRn=15, CRm=3, opc2=0)
>     returns a 32 bits view such that:
>       CBAR = CBAR_EL1[31:18] 0..0 CBAR_EL1[43:32]
>
> This commit fixes the current implementation where:
>   - CBAR_EL1 was returning the 32 bits view instead of the full 64 bits
>     value,
>   - CBAR was returning a truncated 32 bits version of the full 64 bits
>     one, instead of the 32 bits view
>   - CBAR was declared as cp15, opc1=4, CRn=15, CRm=0, opc2=0, which is
>     the CBAR register found in the ARMv7 Cortex-Ax CPUs, but not in
>     ARMv8 CPUs.
>
> Signed-off-by: Luc Michel <address@hidden>
> ---
>  target/arm/helper.c | 6 +++---
>  1 file changed, 3 insertions(+), 3 deletions(-)
>
> diff --git a/target/arm/helper.c b/target/arm/helper.c
> index 507026c915..755aa18a2d 100644
> --- a/target/arm/helper.c
> +++ b/target/arm/helper.c
> @@ -6740,12 +6740,12 @@ void register_cp_regs_for_features(ARMCPU *cpu)
>              ARMCPRegInfo cbar_reginfo[] = {
>                  { .name = "CBAR",
>                    .type = ARM_CP_CONST,
> -                  .cp = 15, .crn = 15, .crm = 0, .opc1 = 4, .opc2 = 0,
> -                  .access = PL1_R, .resetvalue = cpu->reset_cbar },
> +                  .cp = 15, .crn = 15, .crm = 3, .opc1 = 1, .opc2 = 0,
> +                  .access = PL1_R, .resetvalue = cbar32 },

This will break the Cortex-A9 &c which use the 15/0/4/0 encoding
and the un-rearranged value for this register.

I think we need to check through the TRMs to confirm which CPUs use
which format for the CBAR, and have a different feature bit for the
newer format/sysreg encoding, so we can provide the right sysregs for
the right cores.

thanks
-- PMM