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[Qemu-arm] [PATCH v4 59/69] target/arm: Convert T16, nop hints
From: |
Richard Henderson |
Subject: |
[Qemu-arm] [PATCH v4 59/69] target/arm: Convert T16, nop hints |
Date: |
Wed, 4 Sep 2019 12:30:49 -0700 |
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>
---
target/arm/translate.c | 3 +--
target/arm/t16.decode | 17 +++++++++++++++++
2 files changed, 18 insertions(+), 2 deletions(-)
diff --git a/target/arm/translate.c b/target/arm/translate.c
index b70491d39e..69092c12c3 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -10891,8 +10891,7 @@ static void disas_thumb_insn(DisasContext *s, uint32_t
insn)
case 15: /* IT, nop-hint. */
if ((insn & 0xf) == 0) {
- gen_nop_hint(s, (insn >> 4) & 0xf);
- break;
+ goto illegal_op; /* nop hint, in decodetree */
}
/*
* IT (If-Then)
diff --git a/target/arm/t16.decode b/target/arm/t16.decode
index 19a442b894..5829b9a58c 100644
--- a/target/arm/t16.decode
+++ b/target/arm/t16.decode
@@ -19,6 +19,7 @@
# This file is processed by scripts/decodetree.py
#
+&empty !extern
&s_rrr_shi !extern s rd rn rm shim shty
&s_rrr_shr !extern s rn rd rm rs shty
&s_rri_rot !extern s rn rd imm rot
@@ -204,3 +205,19 @@ SETEND 1011 0110 010 1 E:1 000 &setend
REV 1011 1010 00 ... ... @rdm
REV16 1011 1010 01 ... ... @rdm
REVSH 1011 1010 11 ... ... @rdm
+
+# Hints
+
+{
+ YIELD 1011 1111 0001 0000
+ WFE 1011 1111 0010 0000
+ WFI 1011 1111 0011 0000
+
+ # TODO: Implement SEV, SEVL; may help SMP performance.
+ # SEV 1011 1111 0100 0000
+ # SEVL 1011 1111 0101 0000
+
+ # The canonical nop has the second nibble as 0000, but the whole of the
+ # rest of the space is a reserved hint, behaves as nop.
+ NOP 1011 1111 ---- 0000
+}
--
2.17.1
- [Qemu-arm] [PATCH v4 50/69] target/arm: Convert T16 load/store multiple, (continued)
- [Qemu-arm] [PATCH v4 50/69] target/arm: Convert T16 load/store multiple, Richard Henderson, 2019/09/04
- [Qemu-arm] [PATCH v4 53/69] target/arm: Convert T16 branch and exchange, Richard Henderson, 2019/09/04
- [Qemu-arm] [PATCH v4 54/69] target/arm: Convert T16 add, compare, move (two high registers), Richard Henderson, 2019/09/04
- [Qemu-arm] [PATCH v4 63/69] target/arm: Convert T16, Miscellaneous 16-bit instructions, Richard Henderson, 2019/09/04
- [Qemu-arm] [PATCH v4 64/69] target/arm: Convert T16, shift immediate, Richard Henderson, 2019/09/04
- [Qemu-arm] [PATCH v4 66/69] target/arm: Convert T16, Unconditional branch, Richard Henderson, 2019/09/04
- [Qemu-arm] [PATCH v4 57/69] target/arm: Convert T16, Change processor state, Richard Henderson, 2019/09/04
- [Qemu-arm] [PATCH v4 61/69] target/arm: Convert T16, push and pop, Richard Henderson, 2019/09/04
- [Qemu-arm] [PATCH v4 52/69] target/arm: Convert T16 one low register and immediate, Richard Henderson, 2019/09/04
- [Qemu-arm] [PATCH v4 58/69] target/arm: Convert T16, Reverse bytes, Richard Henderson, 2019/09/04
- [Qemu-arm] [PATCH v4 59/69] target/arm: Convert T16, nop hints,
Richard Henderson <=
- [Qemu-arm] [PATCH v4 67/69] target/arm: Convert T16, long branches, Richard Henderson, 2019/09/04
- [Qemu-arm] [PATCH v4 69/69] target/arm: Inline gen_bx_im into callers, Richard Henderson, 2019/09/04
- [Qemu-arm] [PATCH v4 56/69] target/arm: Convert T16, extract, Richard Henderson, 2019/09/04
- [Qemu-arm] [PATCH v4 62/69] target/arm: Convert T16, Conditional branches, Supervisor call, Richard Henderson, 2019/09/04
- [Qemu-arm] [PATCH v4 65/69] target/arm: Convert T16, load (literal), Richard Henderson, 2019/09/04
- [Qemu-arm] [PATCH v4 60/69] target/arm: Split gen_nop_hint, Richard Henderson, 2019/09/04
- [Qemu-arm] [PATCH v4 68/69] target/arm: Clean up disas_thumb_insn, Richard Henderson, 2019/09/04
- Re: [Qemu-arm] [Qemu-devel] [PATCH v4 00/69] target/arm: Convert aa32 base isa to decodetree, no-reply, 2019/09/04