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Re: [Qemu-arm] [PATCH for-4.2 v10 11/15] virtio-iommu: Expose the IOAPIC

From: Tian, Kevin
Subject: Re: [Qemu-arm] [PATCH for-4.2 v10 11/15] virtio-iommu: Expose the IOAPIC MSI reserved region when relevant
Date: Wed, 31 Jul 2019 23:23:26 +0000

> From: Auger Eric [mailto:address@hidden]
> Sent: Thursday, August 1, 2019 3:45 AM
> Hi Michael,
> On 7/31/19 9:25 PM, Michael S. Tsirkin wrote:
> > On Tue, Jul 30, 2019 at 11:20:44PM +0000, Tian, Kevin wrote:
> >>> From: Michael S. Tsirkin [mailto:address@hidden]
> >>> Sent: Wednesday, July 31, 2019 3:38 AM
> >>>
> >>> On Tue, Jul 30, 2019 at 07:21:33PM +0200, Eric Auger wrote:
> >>>> We introduce a new msi_bypass field which indicates whether
> >>>> the IOAPIC MSI window [0xFEE00000 - 0xFEEFFFFF] must be exposed
> >>
> >> it's not good to call it IOAPIC MSI window. any write to this range, either
> >> from IOAPIC or PCI device, is interpreted by the platform as interrupt
> >> request. I'd call it "x86 interrupt address range".
> >
> > Isn't this APIC_DEFAULT_ADDRESS? I'm not sure guests can't change it
> > even though I'm not sure qemu supports changing it.
> That's indeed matching:
> #define APIC_DEFAULT_ADDRESS 0xfee00000
> #define APIC_SPACE_SIZE      0x100000

They are different thing, though value matches. APIC default address
is the memory-mapped region for software to access APIC register. It
can be relocated by the software, with default as 0xfee00000. On the
other hand, the interrupt address range is for root complex to interpret
interrupt message from devices. You can look at Intel SDM 3A, 10.11
Message Signalled Interrupts, where the message address register
format is defined with 0xfee as the hard prefix.


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