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[Qemu-arm] [PATCH 61/67] target/arm: Convert T16, shift immediate
From: |
Richard Henderson |
Subject: |
[Qemu-arm] [PATCH 61/67] target/arm: Convert T16, shift immediate |
Date: |
Fri, 26 Jul 2019 10:50:26 -0700 |
Signed-off-by: Richard Henderson <address@hidden>
---
target/arm/translate.c | 26 ++------------------------
target/arm/t16.decode | 8 ++++++++
2 files changed, 10 insertions(+), 24 deletions(-)
diff --git a/target/arm/translate.c b/target/arm/translate.c
index f3a946d8c9..f9022fe65c 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -10657,7 +10657,7 @@ static void disas_thumb2_insn(DisasContext *s, uint32_t
insn)
static void disas_thumb_insn(DisasContext *s, uint32_t insn)
{
- uint32_t val, op, rm, rd, shift;
+ uint32_t val, rd;
int32_t offset;
TCGv_i32 tmp;
TCGv_i32 tmp2;
@@ -10669,29 +10669,7 @@ static void disas_thumb_insn(DisasContext *s, uint32_t
insn)
/* fall back to legacy decoder */
switch (insn >> 12) {
- case 0: case 1:
-
- rd = insn & 7;
- op = (insn >> 11) & 3;
- if (op == 3) {
- /*
- * 0b0001_1xxx_xxxx_xxxx
- * - Add, subtract (three low registers)
- * - Add, subtract (two low registers and immediate)
- * In decodetree.
- */
- goto illegal_op;
- } else {
- /* shift immediate */
- rm = (insn >> 3) & 7;
- shift = (insn >> 6) & 0x1f;
- tmp = load_reg(s, rm);
- gen_arm_shift_im(tmp, op, shift, s->condexec_mask == 0);
- if (!s->condexec_mask)
- gen_logic_CC(tmp);
- store_reg(s, rd, tmp);
- }
- break;
+ case 0: case 1: /* add/sub (3reg, 2reg imm), shift imm; in decodetree */
case 2: case 3: /* add, sub, cmp, mov (reg, imm), in decodetree */
goto illegal_op;
case 4:
diff --git a/target/arm/t16.decode b/target/arm/t16.decode
index 17297a3032..ddffd073a2 100644
--- a/target/arm/t16.decode
+++ b/target/arm/t16.decode
@@ -126,6 +126,14 @@ ADD_rri 10101 rd:3 ........ \
STM 11000 ... ........ @ldstm
LDM_t16 11001 ... ........ @ldstm
+# Shift (immediate)
+
+@shift_i ..... shim:5 rm:3 rd:3 &s_rrr_shi %s rn=%reg_0
+
+MOV_rrri 000 00 ..... ... ... @shift_i shty=0 # LSL
+MOV_rrri 000 01 ..... ... ... @shift_i shty=1 # LSR
+MOV_rrri 000 10 ..... ... ... @shift_i shty=2 # ASR
+
# Add/subtract (three low registers)
@addsub_3 ....... rm:3 rn:3 rd:3 \
--
2.17.1
- [Qemu-arm] [PATCH 49/67] target/arm: Convert T16 add/sub (3 low, 2 low and imm), (continued)
- [Qemu-arm] [PATCH 49/67] target/arm: Convert T16 add/sub (3 low, 2 low and imm), Richard Henderson, 2019/07/26
- [Qemu-arm] [PATCH 52/67] target/arm: Convert T16 add, compare, move (two high registers), Richard Henderson, 2019/07/26
- [Qemu-arm] [PATCH 54/67] target/arm: Convert T16, extract, Richard Henderson, 2019/07/26
- [Qemu-arm] [PATCH 57/67] target/arm: Convert T16, nop hints, Richard Henderson, 2019/07/26
- [Qemu-arm] [PATCH 51/67] target/arm: Convert T16 branch and exchange, Richard Henderson, 2019/07/26
- [Qemu-arm] [PATCH 60/67] target/arm: Convert T16, Miscellaneous 16-bit instructions, Richard Henderson, 2019/07/26
- [Qemu-arm] [PATCH 53/67] target/arm: Convert T16 adjust sp (immediate), Richard Henderson, 2019/07/26
- [Qemu-arm] [PATCH 56/67] target/arm: Convert T16, Reverse bytes, Richard Henderson, 2019/07/26
- [Qemu-arm] [PATCH 58/67] target/arm: Convert T16, push and pop, Richard Henderson, 2019/07/26
- [Qemu-arm] [PATCH 64/67] target/arm: Convert T16, long branches, Richard Henderson, 2019/07/26
- [Qemu-arm] [PATCH 61/67] target/arm: Convert T16, shift immediate,
Richard Henderson <=
- [Qemu-arm] [PATCH 66/67] target/arm: Move singlestep check from gen_jmp to gen_goto_tb, Richard Henderson, 2019/07/26
- [Qemu-arm] [PATCH 59/67] target/arm: Convert T16, Conditional branches, Supervisor call, Richard Henderson, 2019/07/26
- [Qemu-arm] [PATCH 63/67] target/arm: Convert T16, Unconditional branch, Richard Henderson, 2019/07/26
- [Qemu-arm] [PATCH 62/67] target/arm: Convert T16, load (literal), Richard Henderson, 2019/07/26
- [Qemu-arm] [PATCH 65/67] target/arm: Clean up disas_thumb_insn, Richard Henderson, 2019/07/26
- [Qemu-arm] [PATCH 55/67] target/arm: Convert T16, Change processor state, Richard Henderson, 2019/07/26
- [Qemu-arm] [PATCH 67/67] target/arm: Merge gen_bx_im into trans_BLX_i, Richard Henderson, 2019/07/26
- Re: [Qemu-arm] [Qemu-devel] [PATCH 00/67] target/arm: Convert aa32 base isa to decodetree, no-reply, 2019/07/26