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[Qemu-arm] [PATCH 31/67] target/arm: Convert SVC
From: |
Richard Henderson |
Subject: |
[Qemu-arm] [PATCH 31/67] target/arm: Convert SVC |
Date: |
Fri, 26 Jul 2019 10:49:56 -0700 |
Signed-off-by: Richard Henderson <address@hidden>
---
target/arm/translate.c | 19 +++++++++++++------
target/arm/a32.decode | 4 ++++
2 files changed, 17 insertions(+), 6 deletions(-)
diff --git a/target/arm/translate.c b/target/arm/translate.c
index 3f14e5c7f3..7ea118a795 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -9979,6 +9979,18 @@ static bool trans_BLX_i(DisasContext *s, arg_BLX_i *a)
return true;
}
+/*
+ * Supervisor call
+ */
+
+static bool trans_SVC(DisasContext *s, arg_SVC *a)
+{
+ gen_set_pc_im(s, s->pc);
+ s->svc_imm = a->imm;
+ s->base.is_jmp = DISAS_SWI;
+ return true;
+}
+
/*
* Legacy decoder.
*/
@@ -10243,6 +10255,7 @@ static void disas_arm_insn(DisasContext *s, unsigned
int insn)
case 0x09:
case 0xa:
case 0xb:
+ case 0xf:
/* All done in decodetree. Reach here for illegal ops. */
goto illegal_op;
case 0xc:
@@ -10258,12 +10271,6 @@ static void disas_arm_insn(DisasContext *s, unsigned
int insn)
goto illegal_op;
}
break;
- case 0xf:
- /* swi */
- gen_set_pc_im(s, s->pc);
- s->svc_imm = extract32(insn, 0, 24);
- s->base.is_jmp = DISAS_SWI;
- break;
default:
illegal_op:
gen_illegal_op(s);
diff --git a/target/arm/a32.decode b/target/arm/a32.decode
index f0f0f50c4e..c2fb28f235 100644
--- a/target/arm/a32.decode
+++ b/target/arm/a32.decode
@@ -528,3 +528,7 @@ LDM ---- 100 b:1 i:1 u:1 w:1 1 rn:4 list:16
&ldst_block
B .... 1010 ........................ @branch
BL .... 1011 ........................ @branch
+
+# Supervisor call
+
+SVC ---- 1111 imm:24 &i
--
2.17.1
- [Qemu-arm] [PATCH 19/67] target/arm: Convert Cyclic Redundancy Check, (continued)
- [Qemu-arm] [PATCH 19/67] target/arm: Convert Cyclic Redundancy Check, Richard Henderson, 2019/07/26
- [Qemu-arm] [PATCH 22/67] target/arm: Convert load/store (register, immediate, literal), Richard Henderson, 2019/07/26
- [Qemu-arm] [PATCH 23/67] target/arm: Convert Synchronization primitives, Richard Henderson, 2019/07/26
- [Qemu-arm] [PATCH 24/67] target/arm: Convert USAD8, USADA8, SBFX, UBFX, BFC, BFI, UDF, Richard Henderson, 2019/07/26
- [Qemu-arm] [PATCH 26/67] target/arm: Convert Packing, unpacking, saturation, and reversal, Richard Henderson, 2019/07/26
- [Qemu-arm] [PATCH 28/67] target/arm: Convert MOVW, MOVT, Richard Henderson, 2019/07/26
- [Qemu-arm] [PATCH 25/67] target/arm: Convert Parallel addition and subtraction, Richard Henderson, 2019/07/26
- [Qemu-arm] [PATCH 27/67] target/arm: Convert Signed multiply, signed and unsigned divide, Richard Henderson, 2019/07/26
- [Qemu-arm] [PATCH 29/67] target/arm: Convert LDM, STM, Richard Henderson, 2019/07/26
- [Qemu-arm] [PATCH 30/67] target/arm: Convert B, BL, BLX (immediate), Richard Henderson, 2019/07/26
- [Qemu-arm] [PATCH 31/67] target/arm: Convert SVC,
Richard Henderson <=
- [Qemu-arm] [PATCH 33/67] target/arm: Convert Clear-Exclusive, Barriers, Richard Henderson, 2019/07/26
- [Qemu-arm] [PATCH 38/67] target/arm: Convert Table Branch, Richard Henderson, 2019/07/26
- [Qemu-arm] [PATCH 32/67] target/arm: Convert RFE and SRS, Richard Henderson, 2019/07/26
- [Qemu-arm] [PATCH 36/67] target/arm: Convert PLI, PLD, PLDW, Richard Henderson, 2019/07/26
- [Qemu-arm] [PATCH 35/67] target/arm: Convert SETEND, Richard Henderson, 2019/07/26
- [Qemu-arm] [PATCH 37/67] target/arm: Convert Unallocated memory hint, Richard Henderson, 2019/07/26
- [Qemu-arm] [PATCH 34/67] target/arm: Convert CPS (privileged), Richard Henderson, 2019/07/26
- [Qemu-arm] [PATCH 40/67] target/arm: Convert TT, Richard Henderson, 2019/07/26
- [Qemu-arm] [PATCH 41/67] target/arm: Simplify disas_thumb2_insn, Richard Henderson, 2019/07/26
- [Qemu-arm] [PATCH 43/67] target/arm: Add skeleton for T16 decodetree, Richard Henderson, 2019/07/26