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Re: [Qemu-arm] [Qemu-devel] [PATCH] hw/ssi/xilinx_spips: add lqspi_write
Re: [Qemu-arm] [Qemu-devel] [PATCH] hw/ssi/xilinx_spips: add lqspi_write routine
Thu, 4 Jul 2019 21:12:35 +0200
On [2019 Jul 04] Thu 11:42:54, Peter Maydell wrote:
> On Thu, 4 Jul 2019 at 11:11, Philippe Mathieu-Daudé <address@hidden> wrote:
> > However, looking at the datasheet 'UG1085 (v1.0) November 24, 2015',
> > Chapter 22: Quad-SPI Controller, I understand this region is only
> > accessible by the CPU in READ mode, as an AXI slave.
'Chapter 24: Quad-SPI controllers' in a newer UG1085  says that
writes are ignored and that "All AXI writes generate an external AXI slave
error (SLVERR) on the write response channel" (when speaking of writes to
the linear address memory region). Philip's solution seems correct to me
with the minor change to return MEMTX_ERROR.
> > So, if we model this, even logging LOG_GUEST_ERROR is incorrect, we
> > should trap some AXI bus access error.
> Well, that depends on what the decode and the device really do --
> often datasheets are pretty sloppy and just describe what
> software "should" do, not what the h/w does if software does
> odd things...
> -- PMM