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[Qemu-arm] [PATCH v2 38/42] target/arm: Convert integer-to-float insns t
From: |
Peter Maydell |
Subject: |
[Qemu-arm] [PATCH v2 38/42] target/arm: Convert integer-to-float insns to decodetree |
Date: |
Tue, 11 Jun 2019 11:53:47 +0100 |
Convert the VCVT integer-to-float instructions to decodetree.
Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
---
target/arm/translate-vfp.inc.c | 58 ++++++++++++++++++++++++++++++++++
target/arm/translate.c | 12 +------
target/arm/vfp.decode | 6 ++++
3 files changed, 65 insertions(+), 11 deletions(-)
diff --git a/target/arm/translate-vfp.inc.c b/target/arm/translate-vfp.inc.c
index c50093776b6..cc3f61d9c41 100644
--- a/target/arm/translate-vfp.inc.c
+++ b/target/arm/translate-vfp.inc.c
@@ -2368,3 +2368,61 @@ static bool trans_VCVT_dp(DisasContext *s, arg_VCVT_dp
*a)
tcg_temp_free_i64(vm);
return true;
}
+
+static bool trans_VCVT_int_sp(DisasContext *s, arg_VCVT_int_sp *a)
+{
+ TCGv_i32 vm;
+ TCGv_ptr fpst;
+
+ if (!vfp_access_check(s)) {
+ return true;
+ }
+
+ vm = tcg_temp_new_i32();
+ neon_load_reg32(vm, a->vm);
+ fpst = get_fpstatus_ptr(false);
+ if (a->s) {
+ /* i32 -> f32 */
+ gen_helper_vfp_sitos(vm, vm, fpst);
+ } else {
+ /* u32 -> f32 */
+ gen_helper_vfp_uitos(vm, vm, fpst);
+ }
+ neon_store_reg32(vm, a->vd);
+ tcg_temp_free_i32(vm);
+ tcg_temp_free_ptr(fpst);
+ return true;
+}
+
+static bool trans_VCVT_int_dp(DisasContext *s, arg_VCVT_int_dp *a)
+{
+ TCGv_i32 vm;
+ TCGv_i64 vd;
+ TCGv_ptr fpst;
+
+ /* UNDEF accesses to D16-D31 if they don't exist. */
+ if (!dc_isar_feature(aa32_fp_d32, s) && (a->vd & 0x10)) {
+ return false;
+ }
+
+ if (!vfp_access_check(s)) {
+ return true;
+ }
+
+ vm = tcg_temp_new_i32();
+ vd = tcg_temp_new_i64();
+ neon_load_reg32(vm, a->vm);
+ fpst = get_fpstatus_ptr(false);
+ if (a->s) {
+ /* i32 -> f64 */
+ gen_helper_vfp_sitod(vd, vm, fpst);
+ } else {
+ /* u32 -> f64 */
+ gen_helper_vfp_uitod(vd, vm, fpst);
+ }
+ neon_store_reg64(vd, a->vd);
+ tcg_temp_free_i32(vm);
+ tcg_temp_free_i64(vd);
+ tcg_temp_free_ptr(fpst);
+ return true;
+}
diff --git a/target/arm/translate.c b/target/arm/translate.c
index 05ee76da77c..1e28308aa6a 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -3050,7 +3050,7 @@ static int disas_vfp_insn(DisasContext *s, uint32_t insn)
return 1;
case 15:
switch (rn) {
- case 0 ... 15:
+ case 0 ... 17:
/* Already handled by decodetree */
return 1;
default:
@@ -3063,10 +3063,6 @@ static int disas_vfp_insn(DisasContext *s, uint32_t insn)
if (op == 15) {
/* rn is opcode, encoded as per VFP_SREG_N. */
switch (rn) {
- case 0x10: /* vcvt.fxx.u32 */
- case 0x11: /* vcvt.fxx.s32 */
- rm_is_dp = false;
- break;
case 0x18: /* vcvtr.u32.fxx */
case 0x19: /* vcvtz.u32.fxx */
case 0x1a: /* vcvtr.s32.fxx */
@@ -3181,12 +3177,6 @@ static int disas_vfp_insn(DisasContext *s, uint32_t insn)
switch (op) {
case 15: /* extension space */
switch (rn) {
- case 16: /* fuito */
- gen_vfp_uito(dp, 0);
- break;
- case 17: /* fsito */
- gen_vfp_sito(dp, 0);
- break;
case 19: /* vjcvt */
gen_helper_vjcvt(cpu_F0s, cpu_F0d, cpu_env);
break;
diff --git a/target/arm/vfp.decode b/target/arm/vfp.decode
index 56b8b4e6046..6da9a7913da 100644
--- a/target/arm/vfp.decode
+++ b/target/arm/vfp.decode
@@ -214,3 +214,9 @@ VCVT_sp ---- 1110 1.11 0111 .... 1010 11.0 .... \
vd=%vd_dp vm=%vm_sp
VCVT_dp ---- 1110 1.11 0111 .... 1011 11.0 .... \
vd=%vd_sp vm=%vm_dp
+
+# VCVT from integer to floating point: Vm always single; Vd depends on size
+VCVT_int_sp ---- 1110 1.11 1000 .... 1010 s:1 1.0 .... \
+ vd=%vd_sp vm=%vm_sp
+VCVT_int_dp ---- 1110 1.11 1000 .... 1011 s:1 1.0 .... \
+ vd=%vd_dp vm=%vm_sp
--
2.20.1
- [Qemu-arm] [PATCH v2 22/42] target/arm: Convert VMUL to decodetree, (continued)
- [Qemu-arm] [PATCH v2 22/42] target/arm: Convert VMUL to decodetree, Peter Maydell, 2019/06/11
- [Qemu-arm] [PATCH v2 16/42] target/arm: Convert the VFP load/store multiple insns to decodetree, Peter Maydell, 2019/06/11
- [Qemu-arm] [PATCH v2 24/42] target/arm: Convert VADD to decodetree, Peter Maydell, 2019/06/11
- [Qemu-arm] [PATCH v2 21/42] target/arm: Convert VFP VNMLA to decodetree, Peter Maydell, 2019/06/11
- [Qemu-arm] [PATCH v2 18/42] target/arm: Convert VFP VMLA to decodetree, Peter Maydell, 2019/06/11
- [Qemu-arm] [PATCH v2 19/42] target/arm: Convert VFP VMLS to decodetree, Peter Maydell, 2019/06/11
- [Qemu-arm] [PATCH v2 27/42] target/arm: Convert VFP fused multiply-add insns to decodetree, Peter Maydell, 2019/06/11
- [Qemu-arm] [PATCH v2 23/42] target/arm: Convert VNMUL to decodetree, Peter Maydell, 2019/06/11
- [Qemu-arm] [PATCH v2 25/42] target/arm: Convert VSUB to decodetree, Peter Maydell, 2019/06/11
- [Qemu-arm] [PATCH v2 20/42] target/arm: Convert VFP VNMLS to decodetree, Peter Maydell, 2019/06/11
- [Qemu-arm] [PATCH v2 38/42] target/arm: Convert integer-to-float insns to decodetree,
Peter Maydell <=
- [Qemu-arm] [PATCH v2 32/42] target/arm: Convert VMOV (register) to decodetree, Peter Maydell, 2019/06/11
- [Qemu-arm] [PATCH v2 30/42] target/arm: Convert VNEG to decodetree, Peter Maydell, 2019/06/11
- [Qemu-arm] [PATCH v2 26/42] target/arm: Convert VDIV to decodetree, Peter Maydell, 2019/06/11
- [Qemu-arm] [PATCH v2 36/42] target/arm: Convert VFP round insns to decodetree, Peter Maydell, 2019/06/11
- [Qemu-arm] [PATCH v2 34/42] target/arm: Convert the VCVT-from-f16 insns to decodetree, Peter Maydell, 2019/06/11
- [Qemu-arm] [PATCH v2 33/42] target/arm: Convert VFP comparison insns to decodetree, Peter Maydell, 2019/06/11
- [Qemu-arm] [PATCH v2 40/42] target/arm: Convert VCVT fp/fixed-point conversion insns to decodetree, Peter Maydell, 2019/06/11
- [Qemu-arm] [PATCH v2 37/42] target/arm: Convert double-single precision conversion insns to decodetree, Peter Maydell, 2019/06/11
- [Qemu-arm] [PATCH v2 41/42] target/arm: Convert float-to-integer VCVT insns to decodetree, Peter Maydell, 2019/06/11
- [Qemu-arm] [PATCH v2 35/42] target/arm: Convert the VCVT-to-f16 insns to decodetree, Peter Maydell, 2019/06/11