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Re: [Qemu-arm] [Qemu-devel] [PATCH 08/26] target/arm: Handle SFPA and FP

From: Richard Henderson
Subject: Re: [Qemu-arm] [Qemu-devel] [PATCH 08/26] target/arm: Handle SFPA and FPCA bits in reads and writes of CONTROL
Date: Tue, 23 Apr 2019 14:33:50 -0700
User-agent: Mozilla/5.0 (X11; Linux x86_64; rv:60.0) Gecko/20100101 Thunderbird/60.6.1

On 4/16/19 5:57 AM, Peter Maydell wrote:
> The M-profile CONTROL register has two bits -- SFPA and FPCA --
> which relate to floating-point support, and should be RES0 otherwise.
> Handle them correctly in the MSR/MRS register access code.
> Neither is banked between security states, so they are stored
> in v7m.control[M_REG_S] regardless of current security state.
> Signed-off-by: Peter Maydell <address@hidden>
> ---
>  target/arm/helper.c | 57 ++++++++++++++++++++++++++++++++++++++-------
>  1 file changed, 49 insertions(+), 8 deletions(-)

Reviewed-by: Richard Henderson <address@hidden>


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