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Re: [Qemu-arm] [Qemu-devel] [PATCH V2] target/arm: change arch timer reg

From: Richard Henderson
Subject: Re: [Qemu-arm] [Qemu-devel] [PATCH V2] target/arm: change arch timer registers access permission
Date: Tue, 12 Mar 2019 08:02:06 -0700
User-agent: Mozilla/5.0 (X11; Linux x86_64; rv:60.0) Gecko/20100101 Thunderbird/60.4.0

On 3/12/19 3:30 AM, gengdongjiu wrote:
> From: Dongjiu Geng <address@hidden>
> Some generic arch timer registers are Config-RW in the EL0,
> which means the EL0 exception level can have write permission
> if it is appropriately configured.
> When VM access registers, it firstly checks whether they have RW
> permission, then check whether it is appropriately configured.
> If they are defined to Ready only in EL0, even though they have been
> appropriately configured, they still do not have write permission.
> So need to add the write permission according to ARMV8 spec when
> define it.
> Signed-off-by: Dongjiu Geng <address@hidden>
> ---
> When VM kernel or Hypervisor configures the timer registers to RW in EL0
> user space, it will still have below panic when EL0 user space access
> the timer registers.
> [INFO ]@(el0_sync:60): UNIMPLEMENTED, esr=2000000
> [INFO ]@(unimpl_exception:98): FAR=0000000000000000, ESR=02000000 (EC=0x0, 
> IL=0x1, ISS=0x0)
> [INFO ]@(dump_registers:64): KERNEL REGISTERS
> [INFO ]@(dump_registers:68): X0=00000000f52b7d50 X1=00000000040d5040
> [INFO ]@(dump_registers:68): X2=0000004000033e10 X3=0000000000000000
> [INFO ]@(dump_registers:68): X4=000000007fffffff X5=0000000000000020
> [INFO ]@(dump_registers:68): X6=0000000000000020 X7=000000000c00b030
> ---
>  target/arm/helper.c | 30 +++++++++++++++---------------
>  1 file changed, 15 insertions(+), 15 deletions(-)

Reviewed-by: Richard Henderson <address@hidden>


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