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Re: [Qemu-arm] [PATCH v8 13/13] target/arm: Send interrupts on PMU count
From: |
Richard Henderson |
Subject: |
Re: [Qemu-arm] [PATCH v8 13/13] target/arm: Send interrupts on PMU counter overflow |
Date: |
Fri, 30 Nov 2018 09:13:01 -0800 |
User-agent: |
Mozilla/5.0 (X11; Linux x86_64; rv:60.0) Gecko/20100101 Thunderbird/60.3.1 |
On 11/20/18 1:26 PM, Aaron Lindsay wrote:
> Setup a QEMUTimer to get a callback when we expect counters to next
> overflow and trigger an interrupt at that time.
>
> Signed-off-by: Aaron Lindsay <address@hidden>
> Signed-off-by: Aaron Lindsay <address@hidden>
> ---
> target/arm/cpu.c | 12 +++++
> target/arm/cpu.h | 7 +++
> target/arm/helper.c | 126 +++++++++++++++++++++++++++++++++++++++++---
> 3 files changed, 139 insertions(+), 6 deletions(-)
>
> diff --git a/target/arm/cpu.c b/target/arm/cpu.c
> index 208a08e867..7311a48e3c 100644
> --- a/target/arm/cpu.c
> +++ b/target/arm/cpu.c
> @@ -827,6 +827,13 @@ static void arm_cpu_finalizefn(Object *obj)
> QLIST_REMOVE(hook, node);
> g_free(hook);
> }
> +#ifndef CONFIG_USER_ONLY
> + if (arm_feature(&cpu->env, ARM_FEATURE_PMU) && cpu->pmu_timer) {
No need for two tests here. Just check cpu->pmu_timer.
(If it's set for any reason it should be freed, surely.)
> @@ -1305,7 +1338,18 @@ void pmccntr_op_start(CPUARMState *env)
> eff_cycles /= 64;
> }
>
> - env->cp15.c15_ccnt = eff_cycles - env->cp15.c15_ccnt_delta;
> + uint64_t new_pmccntr = eff_cycles - env->cp15.c15_ccnt_delta;
> +
> + unsigned int overflow_bit = (env->cp15.c9_pmcr & PMCRLC) ? 63 : 31;
> + uint64_t overflow_mask = (uint64_t)1 << overflow_bit;
> + if (!(new_pmccntr & overflow_mask) &&
> + (env->cp15.c15_ccnt & overflow_mask)) {
Fyi, this expression is
env->cp15.c15_ccnt & ~new_pmccntr & overflow_mask
> + env->cp15.c9_pmovsr |= (1 << 31);
> + new_pmccntr &= ~overflow_mask;
Why this line? You just checked that overflow_mask was unset in new_pmccntr
above.
> @@ -1318,13 +1362,28 @@ void pmccntr_op_start(CPUARMState *env)
> void pmccntr_op_finish(CPUARMState *env)
> {
> if (pmu_counter_enabled(env, 31)) {
> - uint64_t prev_cycles = env->cp15.c15_ccnt_delta;
> +#ifndef CONFIG_USER_ONLY
> + uint64_t delta;
> + if (env->cp15.c9_pmcr & PMCRLC) {
> + delta = UINT64_MAX - env->cp15.c15_ccnt + 1;
> + } else {
> + delta = UINT32_MAX - (uint32_t)env->cp15.c15_ccnt + 1;
> + }
FWIW, this is the same as
delta = -env->cp15.c15_ccnt;
if (!(env->cp15.c9_pmcr & PMCRLC)) {
delta = (uint32_t)delta;
}
r~
- [Qemu-arm] [PATCH v8 06/13] target/arm: Implement PMOVSSET, (continued)
- [Qemu-arm] [PATCH v8 06/13] target/arm: Implement PMOVSSET, Aaron Lindsay, 2018/11/20
- [Qemu-arm] [PATCH v8 04/13] target/arm: Filter cycle counter based on PMCCFILTR_EL0, Aaron Lindsay, 2018/11/20
- [Qemu-arm] [PATCH v8 07/13] target-arm: Make PMCEID[01]_EL0 64 bit registers, add PMCEID[23], Aaron Lindsay, 2018/11/20
- [Qemu-arm] [PATCH v8 11/13] target/arm: PMU: Set PMCR.N to 4, Aaron Lindsay, 2018/11/20
- [Qemu-arm] [PATCH v8 12/13] target/arm: Implement PMSWINC, Aaron Lindsay, 2018/11/20
- [Qemu-arm] [PATCH v8 08/13] target/arm: Add array for supported PMU events, generate PMCEID[01]_EL0, Aaron Lindsay, 2018/11/20
- [Qemu-arm] [PATCH v8 09/13] target/arm: Finish implementation of PM[X]EVCNTR and PM[X]EVTYPER, Aaron Lindsay, 2018/11/20
- [Qemu-arm] [PATCH v8 13/13] target/arm: Send interrupts on PMU counter overflow, Aaron Lindsay, 2018/11/20
- Re: [Qemu-arm] [PATCH v8 13/13] target/arm: Send interrupts on PMU counter overflow,
Richard Henderson <=
[Qemu-arm] [PATCH v8 10/13] target/arm: PMU: Add instruction and cycle events, Aaron Lindsay, 2018/11/20