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Re: [Qemu-arm] [PATCH v2 06/11] aspeed/smc: fix default read value
From: |
Cédric Le Goater |
Subject: |
Re: [Qemu-arm] [PATCH v2 06/11] aspeed/smc: fix default read value |
Date: |
Tue, 25 Sep 2018 15:51:22 +0200 |
User-agent: |
Mozilla/5.0 (X11; Linux x86_64; rv:60.0) Gecko/20100101 Thunderbird/60.0 |
On 9/25/18 2:24 PM, Peter Maydell wrote:
> On 21 September 2018 at 17:19, Cédric Le Goater <address@hidden> wrote:
>> 0xFFFFFFFF should be returned for non implemented registers.
>>
>> Also,
>
> Use of "Also" in a commit message often indicates that it
> would be better to split the commit. The two changes here
> don't seem to me to have much to do with each other.
They do in the symptom which is to expose the correct register
values. But I won't argue and next version will introduce two
patches :)
Thanks,
C.
>> the model should expose one control register per possible CS
>> even if there is no flash device attached. When testing the validity
>> of the register number in the read operation, replace 's->num_cs' by
>> 'ctrl->max_slaves' which represents the maximum number of flash
>> devices a controller can handle.
>>
>> Signed-off-by: Cédric Le Goater <address@hidden>
>> ---
>> hw/ssi/aspeed_smc.c | 4 ++--
>> 1 file changed, 2 insertions(+), 2 deletions(-)
>>
>> diff --git a/hw/ssi/aspeed_smc.c b/hw/ssi/aspeed_smc.c
>> index 1270842dcf0c..6045ca11b969 100644
>> --- a/hw/ssi/aspeed_smc.c
>> +++ b/hw/ssi/aspeed_smc.c
>> @@ -665,12 +665,12 @@ static uint64_t aspeed_smc_read(void *opaque, hwaddr
>> addr, unsigned int size)
>> addr == s->r_ce_ctrl ||
>> addr == R_INTR_CTRL ||
>> (addr >= R_SEG_ADDR0 && addr < R_SEG_ADDR0 + s->ctrl->max_slaves) ||
>> - (addr >= s->r_ctrl0 && addr < s->r_ctrl0 + s->num_cs)) {
>> + (addr >= s->r_ctrl0 && addr < s->r_ctrl0 + s->ctrl->max_slaves)) {
>
> The commit message mentions changing the upper bound on the
> address check here and also the unimplemented-register return
> value, but this change also seems to be changing the lower bound
> in the check ?
>
>> return s->regs[addr];
>> } else {
>> qemu_log_mask(LOG_UNIMP, "%s: not implemented: 0x%" HWADDR_PRIx
>> "\n",
>> __func__, addr);
>> - return 0;
>> + return -1;
>> }
>
> thanks
> -- PMM
>
- [Qemu-arm] [PATCH v2 00/11] aspeed: misc fixes and enhancements (SMC), Cédric Le Goater, 2018/09/21
- [Qemu-arm] [PATCH v2 01/11] aspeed/timer: fix compile breakage with clang 3.4.2, Cédric Le Goater, 2018/09/21
- [Qemu-arm] [PATCH v2 02/11] hw/arm/aspeed: change the FMC flash model of the AST2500 evb, Cédric Le Goater, 2018/09/21
- [Qemu-arm] [PATCH v2 03/11] hw/arm/aspeed: Add an Aspeed machine class, Cédric Le Goater, 2018/09/21
- [Qemu-arm] [PATCH v2 04/11] hw/arm/aspeed: add a 'execute-in-place' property to boot directly from CE0, Cédric Le Goater, 2018/09/21
- [Qemu-arm] [PATCH v2 05/11] aspeed/smc: fix some alignment issues, Cédric Le Goater, 2018/09/21
- [Qemu-arm] [PATCH v2 06/11] aspeed/smc: fix default read value, Cédric Le Goater, 2018/09/21
- [Qemu-arm] [PATCH v2 11/11] aspeed/smc: Add dummy data register, Cédric Le Goater, 2018/09/21
- [Qemu-arm] [PATCH v2 10/11] aspeed/smc: inject errors in DMA checksum, Cédric Le Goater, 2018/09/21
- [Qemu-arm] [PATCH v2 09/11] aspeed/smc: add DMA calibration settings, Cédric Le Goater, 2018/09/21
- [Qemu-arm] [PATCH v2 08/11] aspeed/smc: add support for DMAs, Cédric Le Goater, 2018/09/21
- [Qemu-arm] [PATCH v2 07/11] aspeed/smc: add a 'sdram_base' and 'max-ram-size' properties, Cédric Le Goater, 2018/09/21
- Re: [Qemu-arm] [PATCH v2 00/11] aspeed: misc fixes and enhancements (SMC), Peter Maydell, 2018/09/25