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Re: [Qemu-arm] [PATCH 7/9] hw/cpu/a15mpcore: If CPU has EL2, enable it o
From: |
Luc Michel |
Subject: |
Re: [Qemu-arm] [PATCH 7/9] hw/cpu/a15mpcore: If CPU has EL2, enable it on the GIC and wire it up |
Date: |
Wed, 22 Aug 2018 10:27:00 +0200 |
User-agent: |
Mozilla/5.0 (X11; Linux x86_64; rv:60.0) Gecko/20100101 Thunderbird/60.0 |
On 8/21/18 3:28 PM, Peter Maydell wrote:
> For the A15MPCore internal peripheral object, we handle GIC
> security extensions support by checking whether the CPUs
> have EL3 enabled; if so then we enable it also on the GIC.
> Handle the virtualization extensions in the same way: if the
> CPU has EL2 then enable it on the GIC and wire up the
> virtualization-specific memory regions and the maintenance
> interrupt.
>
> Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Luc Michel <address@hidden>
> ---
> hw/cpu/a15mpcore.c | 31 ++++++++++++++++++++++++++++---
> 1 file changed, 28 insertions(+), 3 deletions(-)
>
> diff --git a/hw/cpu/a15mpcore.c b/hw/cpu/a15mpcore.c
> index 43c10794938..226ce8900f2 100644
> --- a/hw/cpu/a15mpcore.c
> +++ b/hw/cpu/a15mpcore.c
> @@ -53,6 +53,7 @@ static void a15mp_priv_realize(DeviceState *dev, Error
> **errp)
> int i;
> Error *err = NULL;
> bool has_el3;
> + bool has_el2;
> Object *cpuobj;
>
> gicdev = DEVICE(&s->gic);
> @@ -67,6 +68,10 @@ static void a15mp_priv_realize(DeviceState *dev, Error
> **errp)
> has_el3 = object_property_find(cpuobj, "has_el3", NULL) &&
> object_property_get_bool(cpuobj, "has_el3", &error_abort);
> qdev_prop_set_bit(gicdev, "has-security-extensions", has_el3);
> + /* Similarly for virtualization support */
> + has_el2 = object_property_find(cpuobj, "has_el2", NULL) &&
> + object_property_get_bool(cpuobj, "has_el2", &error_abort);
> + qdev_prop_set_bit(gicdev, "has-virtualization-extensions", has_el2);
> }
>
> object_property_set_bool(OBJECT(&s->gic), true, "realized", &err);
> @@ -103,20 +108,40 @@ static void a15mp_priv_realize(DeviceState *dev, Error
> **errp)
> qdev_get_gpio_in(gicdev,
> ppibase +
> timer_irq[irq]));
> }
> + if (has_el2) {
> + /* Connect the GIC maintenance interrupt to PPI ID 25 */
> + sysbus_connect_irq(SYS_BUS_DEVICE(gicdev), i + 4 * s->num_cpu,
> + qdev_get_gpio_in(gicdev, ppibase + 25));
> + }
> }
>
> /* Memory map (addresses are offsets from PERIPHBASE):
> * 0x0000-0x0fff -- reserved
> * 0x1000-0x1fff -- GIC Distributor
> * 0x2000-0x3fff -- GIC CPU interface
> - * 0x4000-0x4fff -- GIC virtual interface control (not modelled)
> - * 0x5000-0x5fff -- GIC virtual interface control (not modelled)
> - * 0x6000-0x7fff -- GIC virtual CPU interface (not modelled)
> + * 0x4000-0x4fff -- GIC virtual interface control for this CPU
> + * 0x5000-0x51ff -- GIC virtual interface control for CPU 0
> + * 0x5200-0x53ff -- GIC virtual interface control for CPU 1
> + * 0x5400-0x55ff -- GIC virtual interface control for CPU 2
> + * 0x5600-0x57ff -- GIC virtual interface control for CPU 3
> + * 0x6000-0x7fff -- GIC virtual CPU interface
> */
> memory_region_add_subregion(&s->container, 0x1000,
> sysbus_mmio_get_region(busdev, 0));
> memory_region_add_subregion(&s->container, 0x2000,
> sysbus_mmio_get_region(busdev, 1));
> + if (has_el2) {
> + memory_region_add_subregion(&s->container, 0x4000,
> + sysbus_mmio_get_region(busdev, 2));
> + memory_region_add_subregion(&s->container, 0x6000,
> + sysbus_mmio_get_region(busdev, 3));
> + for (i = 0; i < s->num_cpu; i++) {
> + hwaddr base = 0x5000 + i * 0x200;
> + MemoryRegion *mr = sysbus_mmio_get_region(busdev,
> + 4 + s->num_cpu + i);
> + memory_region_add_subregion(&s->container, base, mr);
> + }
> + }
> }
>
> static Property a15mp_priv_properties[] = {
>
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- [Qemu-arm] [PATCH 0/9] arm: Wire up GICv2 virt support on A15/A7 boards, Peter Maydell, 2018/08/21
- [Qemu-arm] [PATCH 9/9] hw/arm/vexpress: Add "virtualization" property controlling presence of EL2, Peter Maydell, 2018/08/21
- [Qemu-arm] [PATCH 8/9] hw/arm/vexpress: Don't set info->secure_boot if CPU doesn't have EL3, Peter Maydell, 2018/08/21
- [Qemu-arm] [PATCH 7/9] hw/cpu/a15mpcore: If CPU has EL2, enable it on the GIC and wire it up, Peter Maydell, 2018/08/21
- Re: [Qemu-arm] [PATCH 7/9] hw/cpu/a15mpcore: If CPU has EL2, enable it on the GIC and wire it up,
Luc Michel <=
- [Qemu-arm] [PATCH 6/9] hw/arm/fsl-imx6ul: Connect VIRQ and VFIQ, Peter Maydell, 2018/08/21
- [Qemu-arm] [PATCH 5/9] hw/arm/fsl-imx6ul: Connect VIRQ and VFIQ, Peter Maydell, 2018/08/21
- [Qemu-arm] [PATCH 4/9] hw/arm/highbank: Connect VIRQ and VFIQ, Peter Maydell, 2018/08/21
- [Qemu-arm] [PATCH 3/9] hw/arm/vexpress: Connect VIRQ and VFIQ, Peter Maydell, 2018/08/21
- [Qemu-arm] [PATCH 2/9] hw/intc/arm_gic: Make per-cpu GICH memory regions 0x200 bytes large, Peter Maydell, 2018/08/21