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Re: [Qemu-arm] [Qemu-devel] [PATCH v4 5/6] loader: Implement .hex file l
From: |
Stefan Hajnoczi |
Subject: |
Re: [Qemu-arm] [Qemu-devel] [PATCH v4 5/6] loader: Implement .hex file loader |
Date: |
Wed, 15 Aug 2018 18:52:36 +0100 |
On Wed, Aug 15, 2018 at 3:18 PM Philippe Mathieu-Daudé <address@hidden> wrote:
> On 08/13/2018 12:56 PM, Stefan Hajnoczi wrote:
> > On Fri, Aug 10, 2018 at 02:00:44AM -0300, Philippe Mathieu-Daudé wrote:
> >> On 08/03/2018 11:47 AM, Stefan Hajnoczi wrote:
> >>> + parser->rom_start_address = parser->next_address_to_write;
> >>> + parser->current_rom_index = 0;
> >>> + break;
> >>> +
> >>> + case START_SEG_ADDR_RECORD:
> >>> + if (line->byte_count != 4 && line->address != 0) {
> >>> + return -1;
> >>> + }
> >>> +
> >>> + /* x86 16-bit CS:IP segmented addressing */
> >>> + *(parser->start_addr) = (((line->data[0] << 8) | line->data[1])
> >>> << 4) |
> >>> + (line->data[2] << 8) | line->data[3];
> >>
> >> Can you add a qtest for this case?
> >> For the HEX loader I understand the specs as this is the same parsing as
> >> the START_LINEAR_ADDR_RECORD case; so I disagree with data[0] and
> >> data[1] shifts.
> >
> > x86 real-mode CS:IP addressing means (CS << 4) + IP. It produces 24-bit
> > addresses on 80286 and later. This is not the same as
> > START_LINEAR_ADDR_RECORD.
>
> OK!
>
> >
> > GNU bfd implements it as follows:
> >
> > abfd->start_address += (HEX4 (buf) << 4) + HEX4 (buf + 4);
>
> Hmm any idea why they use +4 ?
buf is char* and HEX4("0123") produces 0x0123. So this line evaluates
ASCII hex input buf="XXXXYYYY" to (0xXXXX << 4) + 0xYYYY.
- [Qemu-arm] [PATCH v4 1/6] hw/arm: make bitbanded IO optional on ARMv7-M, (continued)
[Qemu-arm] [PATCH v4 4/6] loader: add rom transaction API, Stefan Hajnoczi, 2018/08/03
[Qemu-arm] [PATCH v4 6/6] Add QTest testcase for the Intel Hexadecimal, Stefan Hajnoczi, 2018/08/03