Re: [Qemu-arm] [Qemu-devel] [PATCH 3/3] aspeed/smc: rename aspeed_smc_flash_send_addr() to aspeed_smc_flash_setup()

[Andrew Jeffery]

On Tue, 12 Jun 2018, at 16:27, Cédric Le Goater wrote:
> Also handle the fake transfers for dummy bytes in this setup
> routine. It will be useful when we activate MMIO execution.
> 
> Signed-off-by: Cédric Le Goater <address@hidden>

Reviewed-by: Andrew Jeffery <address@hidden>

> ---
>  hw/ssi/aspeed_smc.c | 31 ++++++++++++++++---------------
>  1 file changed, 16 insertions(+), 15 deletions(-)
> 
> diff --git a/hw/ssi/aspeed_smc.c b/hw/ssi/aspeed_smc.c
> index b15370893583..b29bfd3124a9 100644
> --- a/hw/ssi/aspeed_smc.c
> +++ b/hw/ssi/aspeed_smc.c
> @@ -503,10 +503,11 @@ static int aspeed_smc_flash_dummies(const 
> AspeedSMCFlash *fl)
>      return dummies;
>  }
>  
> -static void aspeed_smc_flash_send_addr(AspeedSMCFlash *fl, uint32_t addr)
> +static void aspeed_smc_flash_setup(AspeedSMCFlash *fl, uint32_t addr)
>  {
>      const AspeedSMCState *s = fl->controller;
>      uint8_t cmd = aspeed_smc_flash_cmd(fl);
> +    int i;
>  
>      /* Flash access can not exceed CS segment */
>      addr = aspeed_smc_check_segment_addr(fl, addr);
> @@ -519,6 +520,18 @@ static void 
> aspeed_smc_flash_send_addr(AspeedSMCFlash *fl, uint32_t addr)
>      ssi_transfer(s->spi, (addr >> 16) & 0xff);
>      ssi_transfer(s->spi, (addr >> 8) & 0xff);
>      ssi_transfer(s->spi, (addr & 0xff));
> +
> +    /*
> +     * Use fake transfers to model dummy bytes. The value should
> +     * be configured to some non-zero value in fast read mode and
> +     * zero in read mode. But, as the HW allows inconsistent
> +     * settings, let's check for fast read mode.
> +     */
> +    if (aspeed_smc_flash_mode(fl) == CTRL_FREADMODE) {
> +        for (i = 0; i < aspeed_smc_flash_dummies(fl); i++) {
> +                ssi_transfer(fl->controller->spi, 0xFF);
> +        }
> +    }
>  }
>  
>  static uint64_t aspeed_smc_flash_read(void *opaque, hwaddr addr, 
> unsigned size)
> @@ -537,19 +550,7 @@ static uint64_t aspeed_smc_flash_read(void *opaque, 
> hwaddr addr, unsigned size)
>      case CTRL_READMODE:
>      case CTRL_FREADMODE:
>          aspeed_smc_flash_select(fl);
> -        aspeed_smc_flash_send_addr(fl, addr);
> -
> -        /*
> -         * Use fake transfers to model dummy bytes. The value should
> -         * be configured to some non-zero value in fast read mode and
> -         * zero in read mode. But, as the HW allows inconsistent
> -         * settings, let's check for fast read mode.
> -         */
> -        if (aspeed_smc_flash_mode(fl) == CTRL_FREADMODE) {
> -            for (i = 0; i < aspeed_smc_flash_dummies(fl); i++) {
> -                ssi_transfer(fl->controller->spi, 0xFF);
> -            }
> -        }
> +        aspeed_smc_flash_setup(fl, addr);
>  
>          for (i = 0; i < size; i++) {
>              ret |= ssi_transfer(s->spi, 0x0) << (8 * i);
> @@ -586,7 +587,7 @@ static void aspeed_smc_flash_write(void *opaque, 
> hwaddr addr, uint64_t data,
>          break;
>      case CTRL_WRITEMODE:
>          aspeed_smc_flash_select(fl);
> -        aspeed_smc_flash_send_addr(fl, addr);
> +        aspeed_smc_flash_setup(fl, addr);
>  
>          for (i = 0; i < size; i++) {
>              ssi_transfer(s->spi, (data >> (8 * i)) & 0xff);
> -- 
> 2.13.6
> 
>