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[Qemu-arm] [PATCH v5 11/13] target/arm: Implement PMSWINC
From: |
Aaron Lindsay |
Subject: |
[Qemu-arm] [PATCH v5 11/13] target/arm: Implement PMSWINC |
Date: |
Fri, 22 Jun 2018 16:32:25 -0400 |
Signed-off-by: Aaron Lindsay <address@hidden>
---
target/arm/helper.c | 39 +++++++++++++++++++++++++++++++++++++--
1 file changed, 37 insertions(+), 2 deletions(-)
diff --git a/target/arm/helper.c b/target/arm/helper.c
index 3720239..96667e6 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -980,6 +980,15 @@ static bool event_always_supported(CPUARMState *env)
return true;
}
+static uint64_t swinc_get_count(CPUARMState *env)
+{
+ /*
+ * SW_INCR events are written directly to the pmevcntr's by writes to
+ * PMSWINC, so there is no underlying count maintained by the PMU itself
+ */
+ return 0;
+}
+
/*
* Return the underlying cycle count for the PMU cycle counters. If we're in
* usermode, simply return 0.
@@ -1008,6 +1017,10 @@ static uint64_t instructions_get_count(CPUARMState *env)
#define SUPPORTED_EVENT_SENTINEL UINT16_MAX
static const pm_event pm_events[] = {
+ { .number = 0x000, /* SW_INCR */
+ .supported = event_always_supported,
+ .get_count = swinc_get_count
+ },
#ifndef CONFIG_USER_ONLY
{ .number = 0x008, /* INST_RETIRED, Instruction architecturally executed */
.supported = instructions_supported,
@@ -1318,6 +1331,24 @@ static void pmcr_write(CPUARMState *env, const
ARMCPRegInfo *ri,
pmu_op_finish(env);
}
+static void pmswinc_write(CPUARMState *env, const ARMCPRegInfo *ri,
+ uint64_t value)
+{
+ unsigned int i;
+ for (i = 0; i < pmu_num_counters(env); i++) {
+ /* Increment a counter's count iff: */
+ if ((value & (1 << i)) && /* counter's bit is set */
+ /* counter is enabled and not filtered */
+ pmu_counter_enabled(env, i) &&
+ /* counter is SW_INCR */
+ (env->cp15.c14_pmevtyper[i] & PMXEVTYPER_EVTCOUNT) == 0x0) {
+ pmevcntr_op_start(env, i);
+ env->cp15.c14_pmevcntr[i]++;
+ pmevcntr_op_finish(env, i);
+ }
+ }
+}
+
static uint64_t pmccntr_read(CPUARMState *env, const ARMCPRegInfo *ri)
{
uint64_t ret;
@@ -1663,9 +1694,13 @@ static const ARMCPRegInfo v7_cp_reginfo[] = {
.fieldoffset = offsetof(CPUARMState, cp15.c9_pmovsr),
.writefn = pmovsr_write,
.raw_writefn = raw_write },
- /* Unimplemented so WI. */
{ .name = "PMSWINC", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 4,
- .access = PL0_W, .accessfn = pmreg_access_swinc, .type = ARM_CP_NOP },
+ .access = PL0_W, .accessfn = pmreg_access_swinc, .type = ARM_CP_NO_RAW,
+ .writefn = pmswinc_write },
+ { .name = "PMSWINC_EL0", .state = ARM_CP_STATE_AA64,
+ .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 12, .opc2 = 4,
+ .access = PL0_W, .accessfn = pmreg_access_swinc, .type = ARM_CP_NO_RAW,
+ .writefn = pmswinc_write },
{ .name = "PMSELR", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 5,
.access = PL0_RW, .type = ARM_CP_ALIAS,
.fieldoffset = offsetoflow32(CPUARMState, cp15.c9_pmselr),
--
Qualcomm Datacenter Technologies as an affiliate of Qualcomm Technologies, Inc.
Qualcomm Technologies, Inc. is a member of the
Code Aurora Forum, a Linux Foundation Collaborative Project.
- [Qemu-arm] [PATCH v5 04/13] target/arm: Add ARM_FEATURE_V7VE for v7 Virtualization Extensions, (continued)
- [Qemu-arm] [PATCH v5 04/13] target/arm: Add ARM_FEATURE_V7VE for v7 Virtualization Extensions, Aaron Lindsay, 2018/06/22
- [Qemu-arm] [PATCH v5 05/13] target/arm: Remove redundant DIV detection for KVM, Aaron Lindsay, 2018/06/22
- [Qemu-arm] [PATCH v5 06/13] target/arm: Implement PMOVSSET, Aaron Lindsay, 2018/06/22
- [Qemu-arm] [PATCH v5 07/13] target/arm: Add array for supported PMU events, generate PMCEID[01], Aaron Lindsay, 2018/06/22
- [Qemu-arm] [PATCH v5 08/13] target/arm: Finish implementation of PM[X]EVCNTR and PM[X]EVTYPER, Aaron Lindsay, 2018/06/22
- [Qemu-arm] [PATCH v5 09/13] target/arm: PMU: Add instruction and cycle events, Aaron Lindsay, 2018/06/22
- [Qemu-arm] [PATCH v5 10/13] target/arm: PMU: Set PMCR.N to 4, Aaron Lindsay, 2018/06/22
- [Qemu-arm] [PATCH v5 11/13] target/arm: Implement PMSWINC,
Aaron Lindsay <=
- [Qemu-arm] [PATCH v5 13/13] target/arm: Send interrupts on PMU counter overflow, Aaron Lindsay, 2018/06/22
- [Qemu-arm] [PATCH v5 12/13] target/arm: Mark PMINTENSET accesses as possibly doing IO, Aaron Lindsay, 2018/06/22
- Re: [Qemu-arm] [PATCH v5 00/13] More fully implement ARM PMUv3, Peter Maydell, 2018/06/28