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[Qemu-arm] [RISU PATCH v4 16/22] risu_reginfo_aarch64: unionify VFP regs
From: |
Alex Bennée |
Subject: |
[Qemu-arm] [RISU PATCH v4 16/22] risu_reginfo_aarch64: unionify VFP regs |
Date: |
Fri, 22 Jun 2018 15:11:59 +0100 |
This is preparation for the SVE work as we won't want to be carrying
around both VFP and SVE registers at the same time as they overlap.
Signed-off-by: Alex Bennée <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
---
risu_reginfo_aarch64.c | 16 ++++++++--------
risu_reginfo_aarch64.h | 9 ++++++++-
2 files changed, 16 insertions(+), 9 deletions(-)
diff --git a/risu_reginfo_aarch64.c b/risu_reginfo_aarch64.c
index 34dd9af..62a5599 100644
--- a/risu_reginfo_aarch64.c
+++ b/risu_reginfo_aarch64.c
@@ -64,7 +64,7 @@ void reginfo_init(struct reginfo *ri, ucontext_t *uc)
ri->fpcr = fp->fpcr;
for (i = 0; i < 32; i++) {
- ri->vregs[i] = fp->vregs[i];
+ ri->simd.vregs[i] = fp->vregs[i];
}
}
@@ -92,8 +92,8 @@ int reginfo_dump(struct reginfo *ri, FILE * f)
for (i = 0; i < 32; i++) {
fprintf(f, " V%2d : %016" PRIx64 "%016" PRIx64 "\n", i,
- (uint64_t) (ri->vregs[i] >> 64),
- (uint64_t) (ri->vregs[i] & 0xffffffffffffffff));
+ (uint64_t) (ri->simd.vregs[i] >> 64),
+ (uint64_t) (ri->simd.vregs[i] & 0xffffffffffffffff));
}
return !ferror(f);
@@ -138,14 +138,14 @@ int reginfo_dump_mismatch(struct reginfo *m, struct
reginfo *a, FILE * f)
}
for (i = 0; i < 32; i++) {
- if (m->vregs[i] != a->vregs[i]) {
+ if (m->simd.vregs[i] != a->simd.vregs[i]) {
fprintf(f, " V%2d : "
"%016" PRIx64 "%016" PRIx64 " vs "
"%016" PRIx64 "%016" PRIx64 "\n", i,
- (uint64_t) (m->vregs[i] >> 64),
- (uint64_t) (m->vregs[i] & 0xffffffffffffffff),
- (uint64_t) (a->vregs[i] >> 64),
- (uint64_t) (a->vregs[i] & 0xffffffffffffffff));
+ (uint64_t) (m->simd.vregs[i] >> 64),
+ (uint64_t) (m->simd.vregs[i] & 0xffffffffffffffff),
+ (uint64_t) (a->simd.vregs[i] >> 64),
+ (uint64_t) (a->simd.vregs[i] & 0xffffffffffffffff));
}
}
diff --git a/risu_reginfo_aarch64.h b/risu_reginfo_aarch64.h
index a05fb4e..a1c708b 100644
--- a/risu_reginfo_aarch64.h
+++ b/risu_reginfo_aarch64.h
@@ -13,6 +13,10 @@
#ifndef RISU_REGINFO_AARCH64_H
#define RISU_REGINFO_AARCH64_H
+struct simd_reginfo {
+ __uint128_t vregs[32];
+};
+
struct reginfo {
uint64_t fault_address;
uint64_t regs[31];
@@ -24,7 +28,10 @@ struct reginfo {
/* FP/SIMD */
uint32_t fpsr;
uint32_t fpcr;
- __uint128_t vregs[32];
+
+ union {
+ struct simd_reginfo simd;
+ };
};
#endif /* RISU_REGINFO_AARCH64_H */
--
2.17.1
- [Qemu-arm] [RISU PATCH v4 04/22] build-all-arches: do a distclean $(SRC) configured, (continued)
- [Qemu-arm] [RISU PATCH v4 04/22] build-all-arches: do a distclean $(SRC) configured, Alex Bennée, 2018/06/22
- [Qemu-arm] [RISU PATCH v4 06/22] Makefile: include risu_reginfo_$(ARCH) in HDRS, Alex Bennée, 2018/06/22
- [Qemu-arm] [RISU PATCH v4 08/22] risugen: Initialize sve predicates with random data, Alex Bennée, 2018/06/22
- [Qemu-arm] [RISU PATCH v4 07/22] risugen: add --sve support, Alex Bennée, 2018/06/22
- [Qemu-arm] [RISU PATCH v4 09/22] risugen: use fewer insns for aarch64 immediate load, Alex Bennée, 2018/06/22
- [Qemu-arm] [RISU PATCH v4 10/22] risugen: add reg_plus_imm_pl and reg_plus_imm_vl address helpers, Alex Bennée, 2018/06/22
- [Qemu-arm] [RISU PATCH v4 11/22] risugen: add dtype_msz address helper, Alex Bennée, 2018/06/22
- [Qemu-arm] [RISU PATCH v4 16/22] risu_reginfo_aarch64: unionify VFP regs,
Alex Bennée <=
- [Qemu-arm] [RISU PATCH v4 22/22] risu_reginfo_aarch64: handle variable VQ, Alex Bennée, 2018/06/22
- [Qemu-arm] [RISU PATCH v4 14/22] risu: add process_arch_opt, Alex Bennée, 2018/06/22
- [Qemu-arm] [RISU PATCH v4 15/22] risu_reginfo_aarch64: drop stray ;, Alex Bennée, 2018/06/22
- [Qemu-arm] [RISU PATCH v4 21/22] risu_reginfo_aarch64: limit SVE_VQ_MAX to current architecture, Alex Bennée, 2018/06/22
- [Qemu-arm] [RISU PATCH v4 19/22] risu_reginfo_aarch64: add support for copying SVE register state, Alex Bennée, 2018/06/22
- [Qemu-arm] [RISU PATCH v4 20/22] risu_reginfo_aarch64: add SVE support to reginfo_dump_mismatch, Alex Bennée, 2018/06/22
- [Qemu-arm] [RISU PATCH v4 17/22] risu_reginfo: introduce reginfo_size(), Alex Bennée, 2018/06/22
- [Qemu-arm] [RISU PATCH v4 12/22] contrib/generate_all.sh: allow passing of arguments to risugen, Alex Bennée, 2018/06/22